Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2011-03-29
2011-03-29
Le, Thong Q (Department: 2827)
Static information storage and retrieval
Floating gate
Particular biasing
C365S189050, C365S189080, C365S189200, C365S191000, C365S223000
Reexamination Certificate
active
07916553
ABSTRACT:
A processor-based system includes a processor coupled to core logic through a processor bus. This includes a dynamic random access memory (“DRAM”) memory buffer controller. The DRAM memory buffer controller is coupled through a memory bus to a plurality of a dynamic random access memory (“DRAM”) modules and a flash memory module, which are at the same hierarchical level from the processor. Each of the DRAM modules includes a memory buffer to the memory bus and to a plurality of dynamic random access memory devices. The flash memory module includes a flash memory buffer coupled to the memory bus and to at least one flash memory device. The flash memory buffer includes a DRAM-to-flash memory converter operable to convert the DRAM memory requests to flash memory requests, which are then applied to the flash memory device.
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Dorsey & Whitney LLP
Le Thong Q
Micro)n Technology, Inc.
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