Overlay vernier key and method for fabricating the same

Details Overlay vernier key and method for fabricating the same Overlay vernier key and method for fabricating the same

2011-08-16

2011-08-16

Chen, Jack (Department: 2893)

Active solid-state devices (e.g., transistors, solid-state diode

Alignment marks

C257S635000, C257SE23179, C430S005000, C430S022000, C430S030000

Reexamination Certificate

active

07999399

ABSTRACT:
An overlay vernier key includes a semiconductor substrate on which a cell region and a scribe lane region are defined, and a plurality of vernier patterns which are formed in the scribe lane region of the semiconductor substrate and arranged in a polygonal shape. Each of the vernier patterns has a hollow polygonal shape.

REFERENCES:
patent: 2003/0174879 (2003-09-01), Chen
patent: 2006/0263706 (2006-11-01), Yim
patent: 10-2000-0040106 (2000-07-01), None
patent: 10-2003-0089911 (2003-11-01), None
patent: 10-2004-0003936 (2004-01-01), None

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