Semiconductor device

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics

Reexamination Certificate

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C257S758000, C257S774000, C257SE29001, C257SE29343

Reexamination Certificate

active

07915708

ABSTRACT:
A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

REFERENCES:
patent: 5237235 (1993-08-01), Cho et al.
patent: 5583359 (1996-12-01), Ng et al.
patent: 5877533 (1999-03-01), Arai et al.
patent: 7446390 (2008-11-01), Okuda et al.
patent: 2002/0020917 (2002-02-01), Hirota et al.
patent: 2001-177056 (2001-06-01), None
patent: 2001-196536 (2001-07-01), None
patent: 2002-100732 (2002-04-01), None
patent: 2003-152085 (2003-05-01), None
patent: 2005-108874 (2005-04-01), None
Roberto Aparicio, et al., “Capacity Limits and Matching Properties of Integrated Capacitors”, IEEE Journal of Solid-State Circuits, vol. 37, No. 3, Mar. 2002, pp. 384-393.
U.S. Appl. No. 12/485,528, filed Jun. 16, 2009, Okuda, et al.

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