Method and system for innovative substrate/package design...

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor

Reexamination Certificate

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C438S107000, C438S118000, C438S123000, C257S700000, C257S766000, C257S774000, C257S633000, C257S632000, C361S794000, C361S077000, C361S778000

Reexamination Certificate

active

07867816

ABSTRACT:
Provided is a method and system for designing an integrated circuit (IC) substrate, the substrate being formed to include at least one die. The method includes providing at least portions of IC power and a grounding function on a metal 2 substrate layer and utilizing all of a metal 3 substrate layer for the grounding function. Portions of the metal 2 layer and a metal 4 layer are utilized for the IC power, wherein all of the IC power is centralized underneath the die.

REFERENCES:
patent: 5966294 (1999-10-01), Harada et al.
patent: 2003/0149942 (2003-08-01), Hsu
patent: 2004/0183167 (2004-09-01), Hortaleza et al.
patent: 2005/0121771 (2005-06-01), Lin et al.
patent: 2005/0133255 (2005-06-01), Conner et al.
patent: 2005/0235233 (2005-10-01), Hsu
patent: 2006/0157826 (2006-07-01), Lee et al.

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