Computer-aided design and analysis of circuits and semiconductor – Design of semiconductor mask or reticle – Analysis and verification
Reexamination Certificate
2011-03-22
2011-03-22
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Design of semiconductor mask or reticle
Analysis and verification
C716S054000, C716S055000, C716S119000, C700S098000, C700S120000, C700S121000, C430S005000, C378S035000
Reexamination Certificate
active
07913197
ABSTRACT:
According to various embodiments of the invention systems and methods for multiple pattern lithography, wherein a target layout pattern that is not capable of being printed in one lithography step is decomposed into multiple patterns that are printable in one lithography operation and, when appropriate, a continuous junction is utilized for where patterns overlap. In a further embodiment, where a continuous junction is not utilized, a splice is utilized at overlap locations. In yet another embodiment, where splices are utilized for overlap locations, identifying where critical nets are located in the target layout pattern, determining how close a component of the critical net is to a splice, and changing the target layout pattern as to avoid the condition of a component of the critical net being in proximity to a splice. In another embodiment of the invention, where splices are utilized at overlap locations, placing a landing pad of contacts or vias at the same location as the splice.
REFERENCES:
patent: 5059359 (1991-10-01), Hull et al.
patent: 6600965 (2003-07-01), Hull et al.
patent: 56054039 (1981-05-01), None
patent: 01290078 (1989-11-01), None
Kruger Michiel Victor Paul
Liu Anwei
Sezginer Abdurrahman
Staud Wolf
Yenikaya Bayram
Cadence Design Systems Inc.
Kik Phallaka
Sheppard Mullin Richter & Hampton LLP
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