Semiconductor memory device capable of easily performing...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

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Details

C327S162000, C327S158000

Reexamination Certificate

active

07956659

ABSTRACT:
A semiconductor memory device includes a first clock buffer for outputting a first internal clock signal in response to an inverted signal of the system clock signal and for correcting a duty cycle ratio of the first internal clock signal in response to a control signal; a second clock buffer for outputting a second internal clock signal in response to the system clock signal and for correcting a duty cycle ratio of the second internal clock signal in response to the control signal; an analog duty cycle correction circuit for outputting the control signal corresponding to the duty cycle ratio of the first and second internal clock signals; a mixing circuit for mixing the first and second internal clock signals and for outputting a third internal clock signal whose duty cycle is corrected; and a DLL circuit for outputting a delay-locked clock signal by using the third internal clock signal.

REFERENCES:
patent: 6225834 (2001-05-01), Gang
patent: 6377511 (2002-04-01), Okuda et al.
patent: 6452432 (2002-09-01), Kim
patent: 6466071 (2002-10-01), Kim et al.
patent: 6768348 (2004-07-01), Shionoiri et al.
patent: 7199634 (2007-04-01), Cho et al.
patent: 7298180 (2007-11-01), Hung
patent: 10-2004-0090180 (2004-10-01), None
patent: 10-2005-0040551 (2005-05-01), None
patent: 10-2005-0055925 (2005-06-01), None
patent: 10-2005-0079801 (2005-08-01), None

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