Device and method for testing a noise immunity...

Electricity: measuring and testing – Impedance – admittance or other quantities representative of... – Parameter related to the reproduction or fidelity of a...

Reexamination Certificate

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C324S076110, C324S765010

Reexamination Certificate

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07932731

ABSTRACT:
A device for testing noise immunity of a circuit includes: an analog circuit, an internal stable reference signal source, an internal power supply module to receive a high level voltage supply, and a signal modulator to provide a noisy signal to the power supply module. The power supply module outputs a noisy power supply to the circuit, in response to the noisy signal, and the device outputs a signal representative of a noise immunity of the circuit. A method includes: providing a high level supply voltage to an internal power supply module, receiving signals representative of the performance of an analog circuit, providing a noisy signal to an input of the power supply module, providing a noisy supply voltage to the circuit, by the power supply module, in response to the noisy signal, and evaluating a noise immunity characteristic of the circuit in response to the received signals.

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patent: 2005/0122138 (2005-06-01), Chansungsan et al.
patent: 2005/0270199 (2005-12-01), Gupta
patent: 1607835 (2005-12-01), None
patent: 2004309153 (2004-11-01), None
Fefer et al; “Automatic system for VLSI on-chip block synthesizers characterization” Electronics, Circuits and Systems, 2004. ICECS 2004. Proceedings of the 2004 11th IEEE International Conference on Dec. 13-15, 2004 pp. 587-590.

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