Pulse or digital communications – Synchronizers
Reexamination Certificate
2011-02-01
2011-02-01
Payne, David C (Department: 2611)
Pulse or digital communications
Synchronizers
C375S373000, C375S376000
Reexamination Certificate
active
07881413
ABSTRACT:
Phase locked loops (PLL) providing for conditional holdover are especially suited for use in communications networks. During a holdover condition, the timing signal is generated without use of an input reference clock signal. The PLLs may either enter or remain in a holdover condition if the demonstrated or expected quality level of the output of the PLL equals or exceeds the indicated quality level of the input reference clock signal. In this manner, the timing signal has an expected quality level equal to or greater than the quality level of the reference clock signal. Accordingly, network timing errors may be reduced to levels below those associated with using the reference clock signal.
REFERENCES:
patent: 4849993 (1989-07-01), Johnson et al.
patent: 5317601 (1994-05-01), Riordan et al.
patent: 5555247 (1996-09-01), Matsuoka et al.
patent: 5581555 (1996-12-01), Dubberly et al.
patent: 5726607 (1998-03-01), Brede et al.
patent: 5990715 (1999-11-01), Nishimura
patent: 5994934 (1999-11-01), Yoshimura et al.
patent: 6014414 (2000-01-01), Yamamoto et al.
patent: 6049239 (2000-04-01), Eto et al.
patent: 6065140 (2000-05-01), Irwin
patent: 6104915 (2000-08-01), Zhang et al.
patent: 6242954 (2001-06-01), Taniguchi et al.
patent: 6304582 (2001-10-01), Zhang et al.
patent: 6313676 (2001-11-01), Abe et al.
patent: 6323705 (2001-11-01), Shieh et al.
patent: 6356156 (2002-03-01), Wesolowski
patent: 6384649 (2002-05-01), Boerstler et al.
patent: 6424185 (2002-07-01), Wolf
patent: 6441692 (2002-08-01), Nakatani et al.
patent: 6462623 (2002-10-01), Horan et al.
patent: 6542039 (2003-04-01), Ogura
patent: 6943609 (2005-09-01), Zampetti et al.
patent: 2002/0022465 (2002-02-01), McCullagh et al.
patent: 2002/0080901 (2002-06-01), Ham, III
patent: 2002/0097743 (2002-07-01), Baydar et al.
“Timing Characteristics of Primary Reference Clocks”, International Telecommunication Union, ITU-T G.811, Series G: Transmission Systems and Media, Digital Systems and Networks, Digital Transmission Systems—Digital Networks—Design Objectives for Digital Networks, Sep. 1997, pp. 1-4.
“Timing Requirements of Slave Clocks Suitable for use as Node Clocks in Synchronization Networks”, International Telecommunication Union, ITU-T G.812, Series G: Transmission Systems and Media, Digital Systems and Networks, Digital Transmission Systems—Digital Networks—Design Objectives for Digital Networks, Jun. 1998, pp. 1-36.
“Symmetricom's DCD-500 Series Version 5 with SSM”, Symmetricom, Apr. 1999, pp. 1-15.
“Synchronizing Telecommunication Networks, Basic Concepts”, Symmetricom, pp. 1-23, 2001.
“Synchronizing Telecommunications Networks, Fundamentals of Synchronization Planning”, Symmetricom, 2000, pp. 1-23.
“SDH Telecommunications Standard Primer”, Tektronix, Inc., 2000, pp. 1-40.
Green, et al., “Keeping in synch with Sonet: How to manage Sonet networks using Synchronization Status Messages”, America's Network, www.americaasnetwork.com, Sep. 15, 1997, pp. 1-10.
Lesea, “Stratum Levels Defined”, Larus, Timing Booklet, Chapter 4, www.laruscorp.com, 1998, pp. 1-3.
ADC Telecommunications Inc.
Fogg & Powers LLC
Payne David C
Wong Linda
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