Wordline booster design structure and method of operating a...

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing

Reexamination Certificate

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C365S165000

Reexamination Certificate

active

07921388

ABSTRACT:
The invention relates to a wordline booster circuit, especially an SRAM-wordline booster circuit, comprising a driving element (20) for shifting a voltage level of a charge storage element (50) for storing a charge necessary to generate a boosted voltage (Vb), a feedback element (30) for controlling the switching state of a charging element (40), wherein the charging element (40) is actively switchable between a turned-off state during a first time interval and a turned-on state during a second time interval, and an output port (14) for supplying the boost voltage to at least one wordline-driver circuit (100) of a memory device (200). The invention relates also to an operation method for such a wordline booster circuit as well as a memory array implementation on an integrated circuit, especially an SRAM memory array, with a wordline booster circuit.

REFERENCES:
patent: 2002/0116686 (2002-08-01), Shin et al.
Toru Tanazawa and Shigeru Atsumi, in “Optimization of Word-Line Booster Circuits for Low-Voltage Flash Memories”, IEEE Journal of Solid-State Circuits, vol. 34, pp. 1091-1098, Aug. 1999.
John F. Dickson in “On-Chip High-Voltage Generation in MNOS Integrated Circuits using an Improved Voltage Multiplier Technique”, IEEE Journal of Solid-State circuits, vol. 11, pp. 374-378, Jun. 1976, where a voltage multiplier technique has been used for generating high supply voltages.
Jae-Youl Lee, Sung-Eun Kim et al. in “A Regulted Charge Pump with Small Ripple Voltage and Fast Start-Up”, IEEE Journal of Solid-State Circuits, vol. 41, pp. 425-432, Feb. 2006.
N. Otsuka and M. Horowitz in “Circuit Techniques for 1.5-V Power Supply Flash Memory”, IEEE Journal of Solid State Circuits, vol. 32, pp. 1217-1230, Aug. 1997.

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