Processor architecture with wide operand cache

Details Processor architecture with wide operand cache Processor architecture with wide operand cache

2011-05-24

2011-05-24

Washburn, Daniel (Department: 2628)

Computer graphics processing and selective visual display system

Computer graphic processing system

Graphic command processing

C712S001000, C712S220000, C712S225000

Reexamination Certificate

active

07948496

ABSTRACT:
A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.

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