Row addressing

Details Row addressing Row addressing

2011-04-26

2011-04-26

Pham, Ly D (Department: 2827)

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

C365S200000, C365S230060, C711S202000, C711S209000, C711S214000

Reexamination Certificate

active

07933162

ABSTRACT:
Embodiments are provided that include a row decoder, including a row activation path, having a row address converter with an output coupled to an input of a section replacement detector. Further embodiments provide a method including mapping an external row address to an internal row address, wherein the internal row address comprises a section address, determining whether a section corresponding to the section address includes an error, and if the section includes an error, converting the internal row address to a redundant row address, wherein mapping the external row address to the internal row address is initiated prior to determining whether the section replacement should be performed. Further embodiments include a method for receiving a row address for a row in a memory section including a non-2^n number of normal rows and mapping the row address to a redundant row address by substracting a value from the row address.

REFERENCES:
patent: 2005/0174862 (2005-08-01), Watanabe et al.
patent: 2007/0279984 (2007-12-01), Mori et al.
U.S. Appl. No. 12/120,871, filed May 15, 2008, Nakanishi et al.

Affiliated with

Also associated with

Rating

Row addressing does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Row addressing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Row addressing will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2622374