Method of test sequence generation

Details Method of test sequence generation Method of test sequence generation

1990-10-22

1994-04-19

Beausoliel, Jr., Robert W.

Excavating

371 23, 371 221, G06F 1100

Patent

active

053053281

ABSTRACT:
An efficient method of generating test sequences for sequential circuits is disclosed. This method generates a test sequence for a combinational circuit which includes an object fault, examines memory elements where a resulting state (other than "don't care") has been set as a result of the fault. This is followed by fault propagation and state justification. In the event that, due to such factors as limitations in computing time, generation of test sequence was aborted during fault propagation or state justification, the states of the memory elements are provided for determining which memory element should be scanned to detect the fault. In another embodiment an assumed fault from previous processing has been propagated to a memory element and, thus, to a pseudo primary input terminal. The results of the previous processing are used to propagate the fault to a primary output terminal or to another memory element and, thus, to another pseudo primary output terminal. Other embodiments of the invention generate tests according to degrees of difficulty in generating a fault of a particular type along various signal paths in the circuit. These include faults propagated to the control input terminals of memory elements. A final embodiment of the invention determines, as a result of prior processing, values which should be set for a tree circuit input in order to set the tree circuit output to a 0 or a 1. Then, during test generation, when selecting the signal line and the signal to be set, the tree data is used to expedite the selection and processing of signal line and value assignments.

REFERENCES:
patent: 4833395 (1989-05-01), Sasaki et al.
patent: 4903267 (1990-02-01), Arai
patent: 4996689 (1991-02-01), Samad
Essential: An efficient self-learning test-Pattern Generation Algorithm for Sequential Circuits by Michael H. Schulz; Elisabeth Auth; 1989 IEEE pp. 28-37.
Smart & Fast: Test Generation for VLSI Scan-Design Circuits by M. Abramovici; J. J. Kulikowski; P. R. Menon; & D. T. Miller Aug. 1986 IEEE pp. 43-54.
Controllability/Observability Analysis of Digital Circuits by Lawrence H. Goldstein 1979 IEEE pp. 685-693.

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