Testing random access memories

Details Testing random access memories Testing random access memories

1991-02-25

1994-04-19

Baker, Stephen M.

Excavating

G11C 2900

Patent

active

053053273

ABSTRACT:
A method for testing data lines of a random access memory in which two sets of test words are generated such that each test word has a number of bits equal to the number (D) of data lines. The first set has n test words where n is determined by the expression 2.sup.n .gtoreq.D>2.sup.n-1. The test words in the first set have respective designations S=0 to n-1. The bits of each test word are arranged in groups where each group has 2.sup.S number of bits. All of the bits in an individual group have the same binary level and the adjacent groups have bits of the opposite binary level. The second set also has n test words with respective designations S=0 to n-1 and are respectively similar to the test words in the first set except that the binary level of each bit in each test word in the second set is opposite to the binary level of the respective bit of the corresponding test word in the first set. One of the test words from either set is written into each of the address locations of the random access memory. The address locations are then read and it is determined whether each of the read test words is the same as the test word which was written. The above process is repeated until all of the test words in the first set are written and read and only one of the test words in the second set is written and read.

REFERENCES:
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Dekker, R. et al., "Realistic Built-In Self-Test for Static RAMs", IEEE Design & Test of Computers, Feb. 1989, pp. 26-34.
IBM Technical Disclosure Bulletin, vol. 27, No. 4A, Sep. 1984, New York US pp. 1984-1987; D. C. Haigh: Data Patterns for Bus or Ram Checkout.
Proceedings of the International Test Conference, Sep. 1-3, 1987, pp. 759-764, IEEE, New York, US; E. F. Sarkany et al.; Minimal Set of Patterns to Test Ram Components p. 763, right column, line 1- p. 765, left column, line 42.
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