Semiconductor device manufacturing: process – Electron emitter manufacture
Reexamination Certificate
1997-06-18
2001-11-06
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Electron emitter manufacture
C216S011000, C445S050000, C445S051000
Reexamination Certificate
active
06312965
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to field emission displays (FEDs) and to methods for sharpening emitter sites used in FEDs and other electronic equipment.
BACKGROUND OF THE INVENTION
Flat panel displays have recently been developed for visually displaying information generated by computers and other electronic devices. These displays can be made lighter and require less power than conventional cathode ray tube displays. One type of flat panel display is known as a cold cathode field emission display (FED).
A cold cathode FED uses electron emissions to illuminate a cathodoluminescent screen and generate a visual image. A single pixel
10
of a FED is shown in FIG.
1
. The FED includes a baseplate
11
(i.e., substrate) formed with a conductive layer
12
. An emitter site
13
is formed on the conductive layer
12
. The emitter site
13
is typically formed as a sharpened projection having a pointed apex. Alternately the emitter site
13
may be formed as a sharpened edge, as a multi-faceted structure (e.g., pyramidal) having a pointed apex or as an array of points.
A gate electrode structure, or grid
15
, is associated with the emitter site
13
. The grid
15
and baseplate
11
are in electrical communication with a voltage source
20
. When a sufficient voltage differential is established between the emitter site
13
and the grid
15
, a Fowler-Nordheim electron emission is initiated from the emitter site
13
. Electrons
17
emitted at the emitter site
13
impinge on a cathodoluminescent display screen
16
. The display screen
16
includes an external glass face
14
, a transparent electrode
19
and a phosphor coating
21
. The electrons impinging on the phosphor coating
21
increase the energy level of phosphors contained within the coating
21
. When the phosphors return to their normal energy level, photons of light are released to form a visual image.
With a gated pixel
10
, the grid
15
is electrically isolated from the baseplate
11
by an insulating layer
18
. The insulating layer
18
also provides support for the grid
15
and prevents the breakdown of the voltage differential. The insulating layer
18
and grid
15
include a cavity
23
which surrounds the emitter site
13
.
Individual pixels of field emission displays are sometimes referred to as vacuum microelectronic triodes. The triode elements include the cathode (field emitter site), the anode (cathodoluminescent screen) and the gate (grid). U.S. Pat. No. 5,210,472 to Casper et al.; U.S. Pat. No. 5,232,549 to Cathey et al.; U.S. Pat. No. 5,205,770 to Lowrey et al.; U.S. Pat. No. 5,186,670 to Doan et al.; and U.S. Pat. No. 5,229,331 to Doan et al. disclose various methods for forming elements of field emission displays.
Emitter sites for FEDs are typically formed of silicon or a metal such as molybdenum or tungsten. Other conductive materials such as carbon and diamond are also sometimes used. In order to provide a uniform resolution and brightness at the display screen, each emitter site should be uniformly shaped. In addition, emitter sites should be uniformly spaced from the display screen. Accordingly, different methods have been developed in the art for fabricating emitter sites on silicon and other substrates to insure a high degree of uniformity.
As an example, U.S. Pat. No. 5,151,061 to Sandhu, describes a method for forming self-aligned conical emitter sites on a silicon substrate. U.S. Pat. No. 5,259,799 to Doan et al. describes a method for forming self-aligned emitter sites and gate structures for FEDs.
In addition to being uniformly shaped and spaced, the emitter sites should also be sharp to permit optimal electron emission at moderate voltages. The voltage required to generate emission decreases dramatically with increased sharpness. For this reason during the FED fabrication process, thermal oxidation is typically used to sharpen emitter sites. As an example, with emitter sites formed of single crystal silicon, a thermal oxidation process can be used to form a layer of SiO
2
on a silicon projection. This surface oxide is then stripped using a wet etching process.
Improved techniques have been developed recently for oxidation sharpening single crystal silicon emitter sites. One such technique is described in the technical article by Marcus et al. entitled, “Atomically Sharp Silicon and Metal Field Emitters”; IEEE Transactions On Electron Devices, Vol. 38, No. 10, October (1991). In the Marcus et al. process, the emitter sites are 5 &mgr;m-high cones that are oxidation sharpened using a process in which single crystal silicon is thermally oxidized, preferably at a high temperature of 950° C. The emitter sites formed by this process have a radius of curvature at the apex of less than 1 nm. Another method for forming and sharpening single crystal silicon emitter sites is disclosed in U.S. Pat. No. 5,100,355 to Marcus et al. In this method a silicon protuberance is formed and then coated with a material which serves as a mold. The silicon is removed and the mold is filled with a metal. The mold is then removed to leave the metal protuberance.
One problem associated with prior art oxidation sharpening processes for forming emitter sites is that in general, these processes are performed at relatively high temperatures. As an example, for thermal oxidation processes, temperatures are typically on the order of 900°-1100° C. High oxidation temperatures prevent the successful sharpening of emitter sites made from a variety of materials. In general, these high temperature oxidation sharpening processes have been used in the past only with single crystal silicon emitter sites and not amorphous silicon. With emitter sites formed of amorphous silicon, degradation occurs during transformation of the amorphous silicon to polysilicon. At temperatures of about 600° C. and above, amorphous silicon can become polysilicon and generate grain boundaries and oxide fissures in an emitter site. Accelerated oxidation occurs along these grain boundaries and fissures.
A second problem associated with the high temperature oxidation of amorphous silicon is the formation of bumps or asperities on the surface of the emitter site. Again, this may cause a deformed or asymmetrical emitter site having non-uniform emissivity characteristics and poor resolution. In emitter sites that are designed to be symmetric, this results in poor resolution and high grid current.
Materials other than amorphous silicon, which are used in the construction of emitter sites, are also adversely effected by high temperature oxidation. As an example, emitter sites formed of metal, or metal-silicon composites may also experience distortion and grain boundary growth when subjected to high temperature oxidation processes.
Furthermore, high temperature oxidation processes completely preclude the use of some materials for fabricating other components of field emission displays such as baseplates (
11
, FIG.
1
). As an example, float glass materials have relatively low strain and softening temperatures. With float glass, significant strain occurs at about 500° C. and significant softening occurs at about 700° C.
A further problem with high temperature oxidation sharpening processes are their adverse effect on circuit elements associated with the integrated circuitry for the emitter sites. Because the baseplate which contains the emitter sites is formed of various materials having different coefficients of thermal expansion, heating to high temperatures can cause stress failures. Aluminum alloy interconnects and contacts, may soften or flow at the high temperatures required by the oxidation process. In addition, it may sometimes be necessary to further sharpen or resharpen emitter sites in the presence of other circuit elements that may be adversely effected by the high temperatures.
FIGS. 2A and 2B
illustrate the use of a prior art high temperature oxidation process for sharpening emitter sites formed of amorphous silicon. In
FIG. 2A
, an array of conically shaped amorphous silicon emitter sites
13
have been formed on a
Bowers Charles
Chen Jack
Gratton Stephen A.
Micro)n Technology, Inc.
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