Double cycle lock approach in delay lock loop circuit

Details Double cycle lock approach in delay lock loop circuit Double cycle lock approach in delay lock loop circuit

2000-04-25

2001-11-27

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S161000, C365S233100

Reexamination Certificate

active

06323705

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to Synchronous Dynamic Random Access Memories (SDRAMs), and particularly to Delay Lock Loop (DLL) circuitry employed within SDRAMs for obtaining double data rate (DDR) memory access.
2. State of the Art
In conventional synchronous DRAMs, the timing of when output data is made available or is clocked through the output buffer of the memory device is dependent on when valid data is available from the memory cell array. Specifically, in these conventional systems, data output timing is determined by the access time (tAC) and the output hold time (tOH) of the SDRAM. In order to ensure valid data, the output data is synchronized to be clocked from the output buffer during the time interval between tAC and tOH. This is achieved by designing the memory device with a predetermined delayed clock signal for clocking data through the memory device output buffers.
In an alternative SDRAM design, data output is synchronized to the subsequent rising and/or falling edge of the system clock. An example of this type of SDRAM design is a double data rate (DDR) SDRAM. The DDR SDRAM includes delay lock loop (DLL) circuitry for controlling the internal clock of the memory device so as to synchronized data output with the rising/falling edges of the external system clock. The DLL circuitry inserts an optimum delay time between the clock input buffer and the data output buffer making the data switch simultaneously with the external clock.
FIG. 1A
shows a system block diagram of a SDRAM
10
design including DLL circuitry
11
which in response to external clock signal
11
A provides an optimum delayed clock signal
11
B to the output buffer
12
such that the data
12
A from the DRAM core
13
is output from the buffer
12
on the rising and falling edge of the external clock
11
A to provide Output Data signal
12
B.
FIG. 1B
shows a basic prior art digital DLL circuit design
14
including an input receiver buffer
15
for receiving an external clock signal
15
A and providing an internal clock signal
15
B to a Delay Unit circuit
16
. The Delay Unit circuit
16
is adjustably controlled with digital data stored within a shift register
17
. Delay Unit circuit
16
delays the internal clock signal
15
B by the amount programmed into the shift register. Clock signal
16
A is used to clock output buffer
18
such that data
18
A from the DRAM core is clocked through buffer
18
on the subsequent rising and falling edges of the external clock signal
15
A. The DLL circuit further includes a feedback loop having a Phase Detector
19
which detects the phase difference between a feedback clock signal
16
A′ and the internal clock signal
15
B and generates the signals for controlling the shift register to shift left or right thereby increasing or decreasing the delay, respectively. Dummy output buffer
20
and Dummy receiver buffer
21
provide a path for feedback Clk signal
16
A that is equivalent to the path that the external clock signal
15
A passes through to the output of the system. The delay value stored in register
17
is used to control delay unit circuit
16
causing it to provide a delay such that data
18
A is clocked through buffer
18
to the output of the memory device on each of the next rising or falling edge of the external clock signal.
In order to obtain the desired delay value in register
17
the delay lock loop must be set in a lock state in which there is no phase difference between the clock signal
15
B and the feedback clock signal
16
A′, i.e. signals
15
B and
16
A′ have synchronized rising and falling clock edge timing. When signals
15
B and
16
A′ have synchronized timing then signal
15
A and signal
9
also have synchronized timing since the timing of signal
15
A and signal
9
correspond to the timing of signal
15
B and signal
16
A′, respectively, minus the delay time contributed from equivalent delay receivers
15
and
21
. In addition, since the timing of signal
9
is:
timing
Data Out
=timing
15A
+delay
output buffer 18
timing
Data Out
=timing
15A
+delay
dummy output buffer 20
 timing
Data Out
=timing
9
,
an since dummy buffer
20
provides an equivalent delay as output buffer
18
, then the timing of signal
9
is synchronized with the timing of the Data Out Signal. Consequently, since signal
9
is synchronized with both of signals
15
A and the Data Out Signal, then the External Clk Signal
15
A is synchronized with the Data Out Signal when the DLL circuit is in a lock state thereby providing the desired function of synchronizing rising and falling clock edges of the external clock and the output data of the memory system.
The problem with current DLL circuit designs is that, upon start-up, they require a period of time for the feedback loop to obtain the lock state when there is no phase difference between the feedback signal
16
A′ and the internal clock signal
15
B and the timing of the External Clock
15
A is synchronized with the Data Out signal as described above. In this state, an optimum delay value is stored in the shift register
17
. Obtaining a lock state can take as many as
100
-
200
clock cycles. In addition, these clock cycles significantly increase stand-by current consumption.
What would be desirable is to reduce the time it takes for the DLL circuit to obtain a lock state and to minimize stand-by current due to the DLL circuit in DRR SDRAM memory applications.
SUMMARY OF THE INVENTION
A delay lock loop (DLL) circuit and a synchronous memory system with a DLL circuit thereof having a reduced locking period for achieving a fast lock state within the DLL circuit.
In one embodiment, the delay lock loop circuit includes a first path having a first delay unit circuit for receiving an external clock signal and generating a delayed output clock signal corresponding to the external clock signal delayed by the amount of delay time provided by the first delay unit circuit. The first delay unit circuit is controlled by a digital value stored in a shift register such that the delay time provided by the first delay unit circuit can be adjusted by adjusting the digital value in the shift register. The delay lock loop circuit includes a feedback path with a phase detector for detecting the phase difference between the external clock signal and a feedback signal corresponding to the delayed output clock signal which has been fed back through the whole delay path. Dependent on the detected phase difference, the phase detector generates control signals for controlling the shift register so as to adjust the delay value stored in the register to obtain a desired delay time wherein no phase difference is detected.
The delay lock loop circuit further includes a second delay unit circuit which generates a digital value during start-up of the memory system which is used to pre-set the shift register circuit. The second delay unit circuit includes a plurality of individual delay unit elements. The individual elements in the second delay unit circuit are enabled in response to the rising edge of the first clock cycle of the feedback clock signal. Once enabled, a fixed voltage corresponding to a high logic state which is coupled to the first one of the plurality of individual delay units begins to sequentially propagate through the remainder of the individual delay units in the second delay unit circuit and their corresponding outputs. The second delay unit circuit is then disabled in response to a subsequent rising edge of second cycle of the external clock signal thereby stopping the propagation of the high logic state voltage through the second delay unit circuit. The digital value established on the output of the second delay unit circuit during this time interval pre-sets the shift register. The digital value pre-set into the shift register will reflect a digital value for controlling the first delay unit circuit which is in close range to the digital value to obtain the optimum lock state of the DLL

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