Pulse or digital communications – Multilevel – Transmission line
Reexamination Certificate
1998-05-05
2001-02-27
Chin, Stephen (Department: 2734)
Pulse or digital communications
Multilevel
Transmission line
C326S080000
Reexamination Certificate
active
06195397
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a signal transmission and reception device for an integrated circuit, and more particularly, to a signal transmission and reception device for a new wiring system in which a plurality of different signals generated between two functional blocks in an integrated circuit are transmitted on a signal transmission line.
2. Discussion of the Related Arts
Currently, as production techniques of integrated circuits are developed, a number of transistors included in one chip sharply increases. Particularly, as submicron devices are developed, the number of wiring, not only for local interconnections, but also for interconnections between functional blocks sharply increases, increasing a relative importance of the wiring in the entire chip region very high. To solve this problem, layers are stacked for easy of the wiring, which causes problems of difficulty in fabrication and a low yield coming from the multiple layer.
To reduce such wirings, employment of a multiple-valued logic may be considered, in which a signal is made to carry plural signals, disclosed in detail in [K. Wayne Current, “Current-Mode CMOS Multiple-Valued Logic Circuits”, IEEE J. Solid-States Circuits, vol. 29, No. 2, pp. 95-107 February 1994]. In order to employ such a multiple-valued logic, all the functional blocks in the integrated circuit should be re-designed in conformity with the multiple-valued logic. That is, application of the multiple-valued logic to an existing digital circuit design is difficult and has a large power consumption. Therefore, it is necessary to develop a method in which wiring can be reduced while an internal circuit design of an integrated circuit is not changed for reducing an area of the integrated circuit, and a structure of less layers can be employed as the wiring is reduced form a simple fabrication process of the integrated circuit.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a signal transmission and reception device for a new wiring system that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a signal transmission and reception device for a new wiring system, which can reduce an area occupied by wiring.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the signal transmission and reception device for a new wiring system which is for transmission of data between a plurality of function blocks in an integrated circuit, includes one signal transmission line fitted between the function blocks for transmission of signals, a driving circuit for receiving signals from the function blocks through a plurality of internal signal lines, converting combinations of transitions of the signals into encoded signals, and providing the encoded signal to the signal transmission line, and a reception circuit for receiving the encoded signal transmitted from the driving circuit through the signal transmission line decoding the encoded signal into the original plurality of signals, and providing the original plurality of signals to another plurality of function blocks through a plurality of internal signal tines.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5600634 (1997-02-01), Satoh et al.
patent: 5761246 (1998-06-01), Cao et al.
patent: 5864584 (1999-01-01), Cao et al.
“Current-Mode CMOS Multiple-Valued Logic Circuits”, K. Wayne Current, IEEE Journal of Solid-State Circuits, vol. 29, No. 2, Feb. 1994, pp. 95-107.
Chin Stephen
Fleshner & Kim LLP
Hyundai Electronics Co. Ltd.
Park Albert
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