Method for manufacturing a non-volatile memory device

Details Method for manufacturing a non-volatile memory device Method for manufacturing a non-volatile memory device

2000-06-19

2001-11-20

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Having magnetic or ferroelectric component

C438S396000, C438S694000, C438S710000

Reexamination Certificate

active

06319731

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile memory device, and more particularly, to a nonvolatile ferroelectric memory device and a method for manufacturing the same, which are suitable for efficient layout design and cell size reduction.
2. Background of the Related Art
Generally, a nonvolatile ferroelectric memory, i.e., ferroelectric random access memory (FRAM) has data processing speed as much as dynamic random access memory (DRAM) and retains data even in power off. For this reason, the nonvolatile ferroelectric memory has received much attention as a net generation memory device.
The FRAM and DRAM are memory devices which have almost similar structures, and include a ferroelectric capacitor having high residual polarization characteristic. Such residual polarization characteristic permits data not to be erased even if electric field is removed.
FIG. 1
shows hysteresis loop of a general ferroelectric.
As shown in
FIG. 1
, even if polarization organized by electric field removes electric field, data is maintained at a certain amount (d and a states) without being erased due to the presence of residual polarization (or spontaneous polarization).
A nonvolatile ferroelectric memory cell is applied as a memory device by corresponding d, a state to 1, 0, respectively.
A driving circuit of a related art nonvolatile ferroelectric memory device will be described with reference to the accompanying drawings.
FIG. 2
shows unit cell of a related art nonvolatile ferroelectric memory.
As shown in
FIG. 2
, the related art nonvolatile ferroelectric memory includes a bitline B/L formed in one direction, a wordline W/L formed to cross the bitline, a plate line P/L spaced apart from the wordline in the same direction as the wordline, a transistor T
1
whose gate is connected with the wordline and source is connected with the bitline, and a ferroelectric capacitor FC
1
whose first terminal is connected with a drain of the transistor T
1
and second terminal is connected with the plate line P/L.
Data input/output operation of the related art nonvolatile ferroelectric memory device will be described below.
FIG. 3
a
is a timing chart illustrating the operation of write mode of the related art nonvolatile ferroelectric memory device and
FIG. 3
b
is a timing chart illustrating the operation of read mode thereof.
In case of write mode, an externally applied chip enable signal CSBpad is activated from high state to low state. At the same time, if a write enable signal WEBpad is applied from high state to low state, the write mode starts.
Subsequently, if address decoding in the write mode starts, a pulse applied to a corresponding wordline is transited from low state to high state, so that cell is selected.
A high signal in a certain period and a low signal in a certain period are sequentially applied to a corresponding plate line in a period where the wordline is high.
To write a logic value “1” or “0” in the selected cell, a high signal or low signal synchronized with the write enable signal WEBpad is applied to a corresponding bit line.
In other words, a high signal is applied to the bitline, and if the signal applied to the plate line in a period, where the signal applied to the wordline is high, is low, a logic value “1” is written in the ferroelectric capacitor.
A low signal is applied to the bitline, and if the signal applied to the plate line is high, a logic value “0” is written in the ferroelectric capacitor.
Reading operation of data stored in a cell by the above operation of the write mode will be described below.
If an externally applied chip enable signal CSBpad is activated from high state to low state, all of bitlines become equipotential to low voltage by an equalizer signal before a corresponding wordline is selected.
Then, the respective bitline becomes inert and address is decoded. The low signal is transited to the high signal in the corresponding wordline by the decoded address so that a corresponding cell is selected.
The high signal is applied to the plate line of the selected cell to destruct data corresponding to the logic value “1” stored in the ferroelectric memory.
If the logic value “0” is stored in the ferroelectric memory, the corresponding data is not destructed.
The destructed data and the data which is not destructed are output as different values by the aforementioned hysteresis loop principle, so that a sensing amplifier senses the logic value “1” or “0”.
In other words, if the data is destructed, “d” state is transited to “f” state as shown in hysteresis loop of FIG.
1
. If the data is not destructed, “a” state is transited to “f” state. Thus, if the sensing amplifier is enabled after a certain time has elapsed, the logic value “1” is output in case that the data is destructed while the logic value “0” is output in case that the data is not destructed.
As aforementioned, after the sensing amplifier outputs data, to recover the data to original data, the plate line becomes inert from high state to low state at the state that high signal is applied to the corresponding wordline.
The structure of the aforementioned related art nonvolatile ferroelectric memory device and a method for manufacturing the same will be described.
FIG. 4
a
is a layout of the related art nonvolatile ferroelectric memory device.
As shown in
FIG. 4
a
, the related art nonvolatile ferroelectric memory device includes a first active region
41
and a second active region
41
a
which are asymmetrically formed spaced apart from each other, a second wordline W/L
1
formed across the first active region
41
, a second wordline W/L
2
formed across the second active region
41
a
and spaced apart from the first wordline W/L
1
, a first bitline B/L
1
formed across the first and second wordlines at one side of the first active region
41
, a second bitline B/L
2
formed across the first and second wordlines at one side of the second active region
41
a
, a first ferroelectric capacitor FC
1
electrically connected with the first active region and formed over the first and second wordlines W/L
1
and W/L
2
, a second ferroelectric capacitor FC
2
electrically connected with the second active region
41
a
and formed over the first and second wordlines W/L
1
and W/L
2
, a first plate line P/L
1
electrically connected with the first ferroelectric capacitor FC
1
and formed on the first wordline W/L
1
, and a second plate line P/L
2
electrically connected with the second ferroelectric capacitor FC
2
and formed on the second wordline W/L
2
.
FIG. 4
a
is a layout of the related art nonvolatile ferroelectric memory device based on unit cell. In such a related art nonvolatile ferroelectric memory device, the first and second capacitors FC
1
and FC
2
are formed along the bitline, the first plate line P/L
1
is formed on the first wordline W/L
1
,and the second plate line P/L
2
is formed on the second wordline W/L
2
.
The aforementioned related art nonvolatile ferroelectric memory device will be described in detail with reference to
FIG. 4
b.
FIG. 4
b
is a sectional view illustrating a related art nonvolatile ferroelectric memory device taken along line I-I′ of
FIG. 4
a.
As shown in
FIG. 4
b
, the related art nonvolatile ferroelectric memory device includes a substrate
51
in which an active region and a field region are defined, a first wordline
54
and a second wordline
54
a
which are formed on a first insulating layer
53
on the active region and the field region, first source/drain impurity regions
55
and
56
formed at both sides of the first wordline
54
, second source/drain impurity regions (not shown) formed at both sides of the second wordline
54
a
, a second insulating layer
57
formed on an entire surface including the first and second wordlines
54
and
54
a
, having a contact hole to expose the first drain impurity region
56
, a first plug layer
58
a
buried in the contact hole, a first metal layer
59
for connecting the first plug layer
58
a
with a first bitline(not shown), a third insulati

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