Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1998-03-26
2001-02-13
Hjerpe, Richard A. (Department: 2774)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S062000, C345S066000, C345S067000, C345S068000, C345S072000
Reexamination Certificate
active
06188374
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a display device, and more particularly to an improved plasma display panel (PDP) for displaying a picture with the aid of a discharge caused by an alternating current voltage signal. Also, this invention is directed to an improved driving apparatus for the PDP.
2. Description of the Prior Art
Generally, display panels include a cathode ray tube (CRT), a liquid crystal display panel, a plasma display panel (PDP) and so on. The CRT has disadvantages in that its operational voltage is relatively high and that it is difficult to obtain a large-scale screen and a flat screen. The liquid crystal panel has inferior optical characteristics. Otherwise, in comparison to them, the PDP has advantages in that it is not only easy to obtain a large-scale screen and a flat screen, but also it has superior optical characteristics. Recently, the PDP has prevailed in the market owing to such advantages. Further, a plasma display apparatus employing the PDP controls a discharging interval for each picture element or pixel on the PDP, thereby to display moving pictures or still pictures. This plasma display apparatus, however, has a complex circuit configuration and experiences a severe electromagnetic interference, depending upon an electrode structure in the PDP.
An example of a conventional alternating current plasma display apparatus having such drawbacks is shown in FIG.
1
. Referring to
FIG. 1
, the alternating current plasma display apparatus includes a PDP
10
having m×n pixels arranged in a matrix pattern, and a microcomputer
20
for converting picture data containing red (R), green (G), and blue (B)pixel data into panel picture data and for generating control signals. As shown in
FIG. 2
, each of m×n pixels included in the PDP
10
is composed of three color pixel cells, i.e., R, G, and B pixel cells. Thus, the PDP
10
includes m×3n color pixel cells.
Referring now to
FIG. 2
, the m×3n color pixel cells are divided by a compartment wall
13
in a shape of matrix disposed between an upper substrate
11
and a lower substrate
12
. The compartment wall
13
provides a discharging space for each m×n color pixel cells. In the upper substrate
11
, as shown in
FIG. 3
, m Y sustain electrodes YE
1
, YE
2
, . . . , YEm arranged in parallel with respect to the vertical axis and m Z sustain electrodes ZE
1
, ZE
2
, . . . , ZEm arranged in an alternate pattern with respect to the Y sustain electrodes YE
1
, YE
2
, . . . , YEm are defined in such a manner to be unoverlapped with the compartment wall
13
. Thus, one Y sustain electrode YE and one Z sustain electrode ZE are positioned at the upper portion of color pixel cells in one raw, i.e., one raw of discharging spaces. On the other hand, in the lower substrate
13
, as shown in
FIG. 3
, n R, G, and B address electrodes RE
1
, GE
1
, BE
1
, RE
2
, GE
2
, . . . , BEn-
1
, REn, GEn, BEn are defined in a mutually alternate pattern in such a manner to be unoverlapped with the compartment wall
13
. As a result, one R, G or B address electrode RE, GE or BE is positioned at the lower portion of color pixel cells in one column. Each R, G and B address electrodes RE
1
, GE
1
, BE
1
, RE
2
, GE
2
, . . . , BEn-
1
, REn, GEn, BEn causes a discharge between the Y sustain electrodes YE
1
, YE
2
, . . . , YEm and the Z sustain electrodes ZE
1
, ZE
2
, . . . , ZEm. Also, each Y sustain electrode YE
1
, YE
2
, . . . , YEm keeps the discharge caused between it and the Z sustain electrodes ZE
1
, ZE
2
, . . . , ZEm corresponding thereto. A dielectric material layer
15
and a MgO protective film
16
is sequentially disposed on the upper substrate
11
in which Y and Z sustain electrodes YE
1
, YE
2
, . . . , YEm and ZE
1
, ZE
2
, . . . , ZEm are formed. The dielectric material layer
15
is responsible for limiting a discharge current in each color pixel cell. The protective film
16
is responsible for protecting the dielectric material layer
15
and the Y and Z sustain electrodes YE
1
, YE
2
, . . . , YEm and ZE
1
, ZE
2
, . . . , ZEm from a sputtering accompanied during discharging in each color pixel cell. A R fluorescent body layer
14
A is formed on the surface of each R address electrode RE
1
, RE
2
, . . . , REm; a G fluorescent body layer
14
B is formed at the upper portion of each G address electrode GE
1
, GE
2
, . . . , GEm; and a B fluorescent body layer
14
C is formed on the surface of each G address electrode GE
1
, GE
2
, . . . , GEm. The R, G and B fluorescent body layers
14
A,
14
B and
14
C are usually formed to reach the vicinity of the upper end of the compartment wall
13
. A discharge gas
17
is injected into each of color pixel cells divided by the compartment wall
13
, i.e., discharge spaces. This discharge gas emits a light
18
such as ultraviolet lays when a discharge is generated among the Y sustain electrode YE, the Z sustain electrode ZE, and/or the address electrode RE, GE or BE. The R, G and B fluorescent bodies
14
A,
14
B and
14
C brightens by means of the light from the discharge gas
17
, thereby displaying a picture on the PDP
10
.
Returning to
FIG. 1
, panel picture data generated at the microcomputer
20
contains x subfield picture data SF
1
to SFx for on frame picture data corresponding to a single picture. In other words, one frame field picture data consist of x subfield picture data SF
1
to SFx. Each color pixel cell on the PDP
10
is discharged or undischarged by the subfield picture data SF. The x subfield picture data SF
1
to SFx are made by separating x bits of R, G and B pixel data for each bit thereof. Thus, the first subfield picture data SF
1
contain the least significant bits of R, G, and B pixel data; the second subfield picture data SF
2
contain the next order significant bits of R, G, and B pixel data; and the x numbered subfield picture data SFx contain the most significant bits of R, G, and B pixel data.
Further, the plasma display apparatus includes a memory
30
for temporarily storing panel picture data from the microcomputer
20
, and a Y sustain driver
40
and a Z sustain driver
50
for receiving control signals from the microcomputer
20
. The memory
30
stores panel picture data while dividing the same for frame, for subfield (i.e., for bit) and for color thereof. The Y sustain driver
40
is responsive to the control signals from the microcomputer
20
to sequentially drive m Y sustain electrode lines YE
1
, YE
2
, . . . , YEm every subfield. Specifically, the Y sustain driver
40
applies an erase pulse to all the m Y sustain electrode lines YE
1
, YE
2
, . . . , YEm to thereby eliminate electric charges charged into a side wall
13
in the previous subfield, hereinafter referred to as “wall charges”, and then applies a write pulse to all the m Y sustain electrode lines YE
1
, YE
2
, . . . , YEm to thereby uniformly charge wall charges into the side wall
13
of the PDP
10
. Subsequently, the Y sustain driver
40
sequentially applies to the m Y sustain electrode lines YE
1
, YE
2
, . . . , YEm to thereby sequentially drive the color pixel cells on the PDP
10
for one line. To this end, the Y sustain driver
40
includes l Y driving integrated circuit (IC) chips. The l Y driving IC chips drive the m Y sustain electrode lines YE
1
, YE
2
, . . . , YEm while dividing them into three units. Likewise, the Z sustain driver
50
is responsive to the control signals from the microcomputer
20
to sequentially drive m Z sustain electrode lines ZE
1
, ZE
2
, . . . , ZEm every subfield. Specifically, the Z sustain driver
50
applies an erase pulse to all the m Z sustain electrode lines ZE
1
, ZE
2
, . . . , ZEm to thereby eliminate electric charges charged into the side wall in the previous subfield, that is, wall charges, and then applies a write pulse to all the m Y sustain electrode lines YE
1
, YE
2
, . . . , YEm to thereby uniformly charge wall charges into the side wall
13
of the PDP
10
. Subsequently, the Z sustain driver
50
sequentially applies a sust
Fleshner & Kim LLP
Hjerpe Richard A.
LG Electronics Inc.
Tran Henry N.
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