Epitaxially grown lead germanate film and deposition method

Semiconductor device manufacturing: process – Having magnetic or ferroelectric component

Reexamination Certificate

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C438S933000

Reexamination Certificate

active

06190925

ABSTRACT:

BACKGROUND AND SUMMARY OF THE INVENTION
The present invention relates generally to the fabrication of ferroelectric RAM (FeRAM) memory devices and, more particularly, to a method of maximizing the ferroelectric properties of Lead Germanium Oxide (PGO) thin films by epitaxially growing a PGO film with a c-axis orientation on a conductive electrode.
In recent years, the interest in ferroelectric materials for nonvolatile random access memory application (NvRAMs) has intensified. To meet the requirements for these memory applications, ferroelectric capacitors should have small size, low coercive field, high remanent polarization, low fatigue rate, and low leakage current. Some of the candidate ferroelectric materials under investigation for these applications are perovskite ferroelectrics such as PbZr
1−x
Ti
x
O
3
(PZT) or doped PZT, BaTiO
3
, SrTiO
3
, etc. These materials have a high Curie temperature and promising ferroelectrical properties such as large remanent polarization and low coercive field. However, these perovskite ferroelectrics are known to suffer from serious degradation problems such as fatigue (loss of switchable polarization with increasing reversal of polarization), aging, and leakage current, all of which affect the lifetime of the devices.
Many researchers are trying to improve the above-mentioned materials. An alternative approach is to find new ferroelectric materials. SrBi
2
Ta
2
O
9
(SBT) is a one of the new materials, which has fatigue-free properties. However, SBT must be deposited or annealed at temperatures greater than 750° C., which limits its applications.
Ferroelectric thin films for use in non-volatile memories have drawn much attention in recent years due to their bi-stable nature. Most of the studies on Ferroelectric Random Access Memories (FRAMs) have been concentrated on the memory structure with one transistor and one capacitor. The capacitor is made of a thin ferroelectric film sandwiched between two conductive electrodes (usually Pt). The circuit configuration and read/write sequence of this type memory are similar to that of DRAMs except no data refreshing is necessary in FRAMs. Therefore, the stored data are destroyed and must be restored after every reading. This reading process is named destructive read out (DRO). The fatigue problem observed in ferroelectric capacitor, therefore, becomes one of the major obstacles that limit the realization of these memories on a commercial scale. Fatigue is the decrease of switchable polarization (stored nonvolatile charge) with an increased number of switching cycles. The number of switching cycles is the summation of writing and reading pulses.
Another area of interest related to ferroelectric non-volatile memory study is the deposition ferroelectric thin film directly onto the gate area of FET, to form a ferroelectric-gate controlled FET. The ferroelectric-gate controlled device, such as metal-ferroelectric-silicon (MSF) FET, have been studied since the 1950s. Various modified MFSFET structures have been proposed, for example: Metal-Ferroelectric-Insulator-Silicon (MFIS) FET, Metal-Ferroelectric-Metal-Silicon (MFMS) FET, and Metal-Ferroelectric- Metal-Oxide-Silicon (MFMOS) FET. FRAMs with MFSFET structures have two major advantages over the 1T-1C configuration: (1) smaller memory cell territory in MFSFET, and (2) non-destructive read out (NDRO). The latter enables the MFSFET device to be read thousands of times without switching the ferroelectric polarization. Therefore, the fatigue is not the major issue in MFSFET devices.
Regardless the advantages in MFSFET devices over the 1T-1C FRAMs, little progress has been reported in the realization of practical MFSFET devices. This is due to the following reasons: (1) difficulty in depositing good crystalline ferroelectric thin film directly on silicon; (2) difficulty in cleaning; (3) strong retention problems; (4) single transistor arrays are not common; and (5) little theoretical work has been done on MFSFET devices.
From the analysis of MFMOS devices, it can be stated that lower ferroelectric capacitance results in higher memory window and lower programming voltage. Thicker film and lower ∈
r
material can result in lower ferroelectric capacitance. However, a thicker film could increase programming voltage with respect to the switching field. Common oxide ferroelectric materials exhibit higher ∈
r
and T
c
, while non-oxide ferroelectrics exhibit lower ∈
r
and T
c
. Oxide Pb
5
Ge
3
O
11
thin film has very low ∈
r
and moderate T
c
(178° C.). Table I compares the memory window of MFMOS devices with ferroelectric gate of Pb
5
Ge
3
O
11
, PZT and SrBi
2
Ta
2
O
9
thin films. Even though the steady state polarization for Pb
5
Ge
3
O
11
thin film is much lower than that for PZT and SrBi
2
Ta
2
O
9
film films, the memory window for Pb
5
Ge
3
O
11
gate controlled MFMOS device is larger than its counterparts due to its low ∈
r
. The properties of Pb
5
Ge
3
O
11
thin film is listed in Table II.
TABLE I
Memory Windows for MFMOS Devices with Various Ferroelectrics
Ferroelectric
Pb(Zr,Ti)O
3
SrBi
2
Ta
2
O
9
Pb
5
Ge
3
O
11
P
r
(&mgr;C/cm
2
)
15
7
3.5
&egr;
r
1000
280
35
d
Ferro
(Å)
2000
2000
2000
V
dep
(V)
3.14
4.39
6.87
P
r
* (&mgr;C/cm
2
)
2.4
0.8
0.25
when V
dep
= 0.5 V
Memory Window
1.08
1.29
3.23
2P
r
*/C
F
(V)
Gate oxide (SiO
2
) thickness: 100 Å
Steady state V
dep
is assumed to be 0.5 V
TABLE II
Comparison Various Ferroelectric Thin Films
Material
Pb(Zr
&khgr;
Ti
1−&khgr;
)O
3
SrBi
2
(Ta
&khgr;
Nb
1−&khgr;
)O
9
Pb
5
Ge
3
O
11
&egr;
r
>800
<300
30-50
P
r
(&mgr;C/cm
2
)
15-35
4-11
3.5
T
C
~350° C.
~300° C.
178° C.
Melting Point
>1200° C.
>1200° C.
738° C.
d
33
(CN
−1
)
2.1 × 10
−10
in between
6.2 × 10
−12
CVD Deposition
600-700° C.
700-800° C.
450-650° C.
Temperature
Post Anneal
no
yes
no
Fatigue
Pt: Yes
no
no
RuO
2
: No
Structure
Perovskite
Layered Perovskite
P3
Domain Walls
180°, 90°, 70.5°,
180°, 90°
180°
60°
Prefer
MgO, SrTiO
3
,
??
c-axis prefer
Orientation
Al
2
O
3
orientation
on oriented
Ir and Pt
The above-mentioned comparison of films shows that PGO thin films have advantages in terms of low deposition temperatures, fatigue characteristics, and retention properties.
Ferroelectric thin films are usually oxide ceramics with high melting temperatures. Therefore, it is very difficult to reduce the deposition temperature lower than 600° C. and still maintain the desired phases. This relationship holds regardless of deposition technique. For the most studied PZT thin films, for example, good electrical properties in conjunction with deposition temperatures below 600° C. have not been reported. This problem could be due to metastable pyrochlore phases which tend to form in this temperature range. Although low temperature deposition are possible with improved precursors, or using plasma to enhance the dissociation of precursors, very research in this area has been reported. Recently, the fatigue-free bi-layered ferroelectrics, namely SrBi
2
Ta
2
O
9
or SrBi
2
Nb
2
O
9
, have been produced by MOCVD, sol-gel and pulse laser deposition. However, the deposition temperatures are still greater than 700° C. Further, CVD bi-layered ferroelectric thin films need post-annealing temperatures higher than 700° C. for long time (>1 hr) in order to obtain ferroelectricity.
An alternate method of solving the deposition temperature problem is to use alternate ferroelectric materials. PGO is a natural candidate because of its very low melting temperature (738° C.). At room temperature, the uniaxial ferroelectric PGO system with its polar direction parallel to the c-axis, belongs to the trigonal crystal class (point group: P
3
). This material transforms to the hexagonal (point group: P
6
) paraelectric phase above the Curie temperature (T
C
=178° C.).
Thin films of PGO were made by thermal evaporation, flash-evaporation, and dc reactive sputtering methods. Polycrystalline films with partial c-axis orientation on n-type Si substrates

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