Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
1999-10-22
2001-02-20
Picardàt, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C438S109000, C438S111000, C438S112000
Reexamination Certificate
active
06190946
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor package and, more particularly, to a structure and a fabricating method of a semiconductor package, which is simple in the fabricating process and suitable for improving a reliability of a device.
2. Discussion of the Related Art
In fabrication of a semiconductor package, in general, successive steps of a process are conducted, including dicing for separating chips or integrated circuits fabricated on a wafer, chip bonding for setting the separated chips on paddles in a lead frame, wire bonding for electrically connecting bonding pads on the chips and inner leads of the lead frame, and molding the circuit for protection.
A conventional semiconductor package will be explained with reference to the attached drawing.
FIG. 1
illustrates a sectional structure of a conventional wire bonding semiconductor package.
Referring to
FIG. 1
, the conventional semiconductor package includes a chip
11
with a built-in semiconductor circuit, a lead frame
12
connected to and for supporting the chip
11
, a double sided adhesive tape
13
for fixing the chip
11
and the lead frame
12
, lower pads
15
formed below the lead frame
12
for connecting a PCB (Printed Circuit Board)
14
and the lead frame
12
, bonding pads
16
formed on upper portions of the chip
11
for acting as electrodes, wires
17
for electrically connecting of the boding pads
16
to the lead frame
12
, and a body
18
of EMC (Epoxy Mold Compound) for protecting the device from external environment.
The aforementioned conventional semiconductor package has the following problems.
First, the wire boding process for electrical connection of the chip to the lead frame causes the fabrication process to be complicated and requires a complicated soldering process following the step of stacking the chips.
Second, no heat sinks are provided for dissipation of heat generated during the device operation such that electrical shorts or heating of the semiconductor device may occur.
Third, the conventional semiconductor package is configured such that the packages stacked up on top of each other do not appear very attractive and stable.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a structure and a fabricating method of a semiconductor package that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a method for fabricating a semiconductor package, which has simple in fabrication and easy in stacking.
Another object of the present invention is to provide a structure of a semiconductor package which has a heat sink attached thereon for ease of heat dissipation, that improves the reliability of the device.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the structure of a semiconductor package includes a structure having conductor pieces each buried in one of holes opened through the structure in regular intervals, and a TAB having lead lines fixed at a fixture and extended in four directions each for electrical connection to one of the conductor pieces.
In another aspect of the present invention, there is provided a method for fabricating a semiconductor package including the steps of providing a structure according to a shape of a package, attaching lead lines on a fixture and extending in four directions to form a TAB, forming holes in regular intervals in the structure, burying a piece of conductor in each of the holes, reflowing the lead lines on the TAB for electrical connection of the lead lines to respective pieces of conductor and subsequent attachment of the lead lines to the structure.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5057456 (1991-10-01), Dehaine
patent: 5198888 (1993-03-01), Sugano et al.
patent: 5519936 (1996-05-01), Andros et al.
patent: 5756377 (1998-05-01), Ohsawa
patent: 5763939 (1998-06-01), Yamashita
patent: 5804872 (1998-09-01), Miyano et al.
patent: 5843215 (1998-12-01), Tsukagoshi et al.
patent: 5856212 (1999-01-01), Chun
Hyundai Electronics Industries Co,. Ltd.
Picardat Kevin M.
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