Non-volatile semiconductor memory device

Details Non-volatile semiconductor memory device Non-volatile semiconductor memory device

2000-09-06

2001-10-23

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185180, C365S185170

Reexamination Certificate

active

06307785

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electrically rewritable nonvolatile semiconductor device (EEPROM) and particularly to an EEPROM in which a multi-value memory larger than one bit is stored in one memory cell.
2. Description of the Related Art
As one of electrically rewritable nonvolatile semiconductor memory devices (EEPROM), an NAND type EEPROM in which a high integration can be made is known. In this type of EEPROM, each of a plurality of memory cells has an n-channel FETMOS structure having a floating gate, as a charge storage layer, and a control gate. Then, adjacent memory cells have a source and a drain in which are shared, and is connected in series. The memory cells connected in this manner are to a bitline as one unit. A memory cell array is integrated on a p-type substrate or a p-type well formed on an n-type substrate. The drain side of an NAND cell is connected to the bitline through a select gate, and the source side is connected to a common source line through the select gate. The control gates of the memory cells are sequentially formed in a row direction, and used as a word line.
FIG. 1A
is a plan view showing one NAND cell portion of the memory cell array, and
FIG. 1B
is an equivalent circuit diagram.
FIG. 2A
is a cross-sectional view taken along line of
2
A—
2
A of
FIG. 1A
, and
FIG. 2B
is a cross-sectional view taken along line of
2
B—
2
B of FIG.
1
A.
A memory cell array having a plurality of NAND cells is formed on a p-type silicon substrate
11
(or p-type well), which is surrounded with a device isolation oxide film
12
. In this example, one NAND cell comprises eight memory cells M
1
to M
8
, which are connected in series. Each of the memory cells comprises a floating gate (
14
1
to
14
8
) and a control gate
16
(
16
1
to
16
8
). Each floating gate
14
is formed on the substrate
11
through a tunnel insulating film
13
, and each control gate
16
is formed thereon through a gate insulating film
15
. An n-type diffusion layer
19
is used as both source and drain, and the adjacent memory cells use the n-type diffusion in common so as to be connected in series.
First select gates
14
9
and
16
9
are provided at the drain side of the NAND cell, and second select gates
14
10
and
16
10
are provided at the source side of the NAND cell. The first select gates
14
9
and
16
9
are formed at the same time with the floating gates of the memory cells and the control gates. The above-formed substrate is covered with a CVD oxide film
17
, and a bitline
18
is formed thereon. The control gates
16
of the NAND cell are provided as control gates CG
1
to CG
8
in common. These control gates are used as word lines.
The select gates
14
9
,
16
9
and
14
10
,
16
10
are sequentially formed in a row direction, and used as select gate SG
1
and SG
2
, respectively.
FIG. 3
shows an equivalent circuit of the memory cell array having such NAND cells arranged in a matrix form. One source line per 64 bitlines is connected a substrate voltage line of Al, polysilicon, etc., through a contact. The substrate voltage line is connected to a peripheral circuit. The control gates of the memory cell and the first and second select gates are sequentially formed in a row direction. Normally, a set of memory cells, in which a plurality of the memory cells are connected to the control gates, is called as one page. Then, a set of pages, which are sandwiched between a pair of select gates (first selection gate on the drain side and second select gate on the source side) is called one NAND block or simply one block.
An operation of an NAND cell type EEPROM will be explained as follows.
The data write operation is performed from the memory cell, which is far from the bitline, in order. A boosted voltage Vpp (=about 20V) is applied to the control gate of the selected memory cell. An intermediate voltage Vm (=about 10V) is applied to the control gates of the other non-select memory cells and the first select gate. 0V (“0” state) or an intermediate potential (“1” state) is applied to the bitline in accordance with data. At this time, the potential of the bitline is transmitted to the select cell. At the time of “0” state, a high voltage is applied to the floating gate of the select memory cell and the substrate. As a result, an electron is tunnel-injected to the floating gate from the substrate, and a threshold voltage is moved to a positive direction. At the time of “1” state, the threshold voltage is unchanged.
Data erasing is performed by the block unit at substantially the same time. Specifically, all control gates of the blocks to be erased and the select gates are set to “0” state, and a boosted voltage VppE (about 20V) is applied to a p-type well and an n-type substrate. VppE is also applied to the control gates of the blocks and the select gates, which no erasing is performed. As a result, in the memory cells of the erasing blocks, the electron of the floating gate is discharged to the well and the threshold voltage is moved to the a negative direction.
A data read operation is performed as follows.
Specifically, the control gate of the selected memory cell is set to “0” state, and the control gates of the other memory cells are set to a power-supply voltage Vcc (e.g., 3V). Then, the data read operation is performed by detecting whether a current flows into the select memory cell or not. In a NAND cell type EEPROM, since the plurality of memory cells are connected in a cascade form, an amount of cell currents is small at the reading time. Moreover, since the control gate of the memory cell and the first and second select gates are continuously arranged in a row direction, data for one page is simultaneously read to the bitline.
Because of the limitation of the read operation, the threshold voltage after write “1” state must be controlled to be between 0V to Vcc. Due to this, a verify write is performed, only a memory cell in which “1” is insufficiently written is detected. Then, rewrite data is provided to execute a rewrite operation of only the memory cell in which “1” is insufficiently written (verify write of each bit). The selected control gate is set to, for example, 0.5V (verify voltage) to execute the verify read, so as to detect the memory cell in which “1” insufficiently written.
In other words, if the threshold voltage of the memory cell is not 0.5V or more, the current flows into the select memory cell, and the memory cell is detected as the memory cell in which “1” is insufficiently written. The current naturally flows into the memory cell of “0” state. Due to this, a verify circuit for compensating for the current flowing into the memory cell is provided so that the memory cell is not erroneously recognized as the memory cell in which “1” insufficiently is written. A write verify is performed at a high speed by the verify circuit.
The write and the write verify operations are repeated to execute the data write operation, so that write time of each memory cell is optimized, and the threshold voltage after write “1” must be controlled to be between 0V to Vcc.
In the above-explained NAND cell type EEPROM, there is proposed a multi-value memory cell storing three data “0”, “1”, “2” or more in a state after write operation (FIG.
4
A). In this case, for example, in a “0” state, the threshold voltage is set to be negative. In a “1” state, the threshold voltage is set to from 0V to Vcc/2. In a “2” state, she threshold voltage is set from Vcc/2 to Vcc.
FIG. 4B
shows a conventional verify read operation to check whether or not write operation is sufficiently is performed in this type of ternary memory cell.
In the write operation, after a write voltage (vpp) is applied to the control gate of the memorhy cell (steps S
1
, S
2
), a first verify read cycle (step S
4
) and a second verify read cycle (step S
5
) are sequentially performed. The first verify read cycle checks whether or not “2” state is sufficiently written, and the second verify read cycle checks whether or not “1” stat

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