Integrated circuits and methods for their fabrication

Details Integrated circuits and methods for their fabrication Integrated circuits and methods for their fabrication

1998-05-22

2001-02-06

Dutton, Brian (Department: 2823)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C257S690000, C257S737000, C257S738000, C257S780000, C257S781000

Reexamination Certificate

active

06184060

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to integrated circuits, and more particularly to chip interconnection and to forming contact pads on the back side of a semiconductor chip, and also to thinning of integrated circuits after circuit elements have been fabricated.
Some techniques for forming contacts on the chip “second” side are disclosed in U.S. Pat. No. 5,270,261 issued Dec. 14, 1993 to Bertin et al. and entitled “Three Dimensional Multichip Package Methods of Fabrication”. Alternative techniques are desired.
SUMMARY
The invention provides methods for making back-side contact pads in a semiconductor die (or “chip”). The back-side contact pads are suitable for connecting the die to an underlying die to form a multi-die vertical integrated circuit. The invention also provides vertical integrated circuits. In addition, the invention provides methods for thinning of individual dice whether or not the dice will be part of a vertical integrated circuit.
In some embodiments of the present invention, back-side contact pads are formed as follows. A masked etch of the face side of a semiconductor wafer creates a via over each location where a back-side contact pad is to be formed. A dielectric is deposited over the via, and a conductive layer (for example, metal) is deposited over the dielectric. The bottom portion of the conductive layer in each via will form the back-side contact pad.
After the integrated circuit has been formed, the wafer is etched from the back side until the back-side contact pad is exposed. The etch etches the wafer substrate faster than it etches the dielectric separating the substrate from the pad. Therefore, the wafer substrate is receded relative to the dielectric so that the dielectric protrudes down relative to the substrate around each back-side contact pad. Thus the dielectric insulates the back-side contact pads from the substrate.
In some embodiments, the wafer is held by a non-contact wafer holder during the back-side etch. The face side of the wafer does not physically contact the holder. Therefore, there is no need to cover the face side with any protective layer to protect the wafer during the etch. Further, the holder protects the face side circuitry from the etch.
The wafer is diced into dice before or after the back-side etch.
In some embodiments, the back-side contact pads are used for vertical integration.
In some embodiments, the dice are not used for vertical integration. The dice are thinned to reduce their vertical dimension.
Other embodiments and variations are within the scope of the invention.


REFERENCES:
patent: 3810129 (1974-05-01), Behman et al.
patent: 3811117 (1974-05-01), Anderson, Jr. et al.
patent: 3881884 (1975-05-01), Cook et al.
patent: 3993917 (1976-11-01), Kalter
patent: 4368106 (1983-01-01), Anthony
patent: 4394712 (1983-07-01), Anthony
patent: 4463336 (1984-07-01), Black et al.
patent: 4467518 (1984-08-01), Bansal et al.
patent: 4603341 (1986-07-01), Bertin et al.
patent: 4628174 (1986-12-01), Anthony
patent: 4722130 (1988-02-01), Kimura et al.
patent: 4769738 (1988-09-01), Nakamura et al.
patent: 4807021 (1989-02-01), Okamura
patent: 4842699 (1989-06-01), Hua et al.
patent: 4897708 (1990-01-01), Clements
patent: 4954458 (1990-09-01), Reid
patent: 4978639 (1990-12-01), Hua et al.
patent: 4996587 (1991-02-01), Hinrichsmeyer et al.
patent: 5071792 (1991-12-01), Van Vonno et al.
patent: 5160987 (1992-11-01), Pricer et al.
patent: 5166097 (1992-11-01), Tanielian
patent: 5191405 (1993-03-01), Tomita et al.
patent: 5270261 (1993-12-01), Bertin et al.
patent: 5307942 (1994-05-01), Quelfeter et al.
patent: 5309318 (1994-05-01), Beilstein, Jr. et al.
patent: 5313097 (1994-05-01), Haj-Ali-Ahmadi et al.
patent: 5314844 (1994-05-01), Imamura
patent: 5322816 (1994-06-01), Pinter
patent: 5340771 (1994-08-01), Rostoker
patent: 5380681 (1995-01-01), Hsu
patent: 5399898 (1995-03-01), Rostoker
patent: 5414637 (1995-05-01), Bertin et al.
patent: 5426566 (1995-06-01), Beilstein, Jr. et al.
patent: 5463246 (1995-10-01), Matsunami
patent: 5466634 (1995-11-01), Beilstein, Jr. et al.
patent: 5467305 (1995-11-01), Bertin et al.
patent: 5468663 (1995-11-01), Bertin et al.
patent: 5478781 (1995-12-01), Bertin et al.
patent: 5489554 (1996-02-01), Gates
patent: 5494832 (1996-02-01), Lehmann et al.
patent: 5502333 (1996-03-01), Bertin et al.
patent: 5502667 (1996-03-01), Bertin et al.
patent: 5506753 (1996-04-01), Bertin et al.
patent: 5517057 (1996-05-01), Beilstein, Jr. et al.
patent: 5517754 (1996-05-01), Beilstein, Jr. et al.
patent: 5532519 (1996-07-01), Bertin et al.
patent: 5550942 (1996-08-01), Sheem
patent: 5561622 (1996-10-01), Bertin et al.
patent: 5563086 (1996-10-01), Bertin et al.
patent: 5567653 (1996-10-01), Bertin et al.
patent: 5567654 (1996-10-01), Beilstein, Jr. et al.
patent: 5571754 (1996-11-01), Bertin et al.
patent: 5596226 (1997-01-01), Beilstein, Jr. et al.
patent: 5843844 (1998-12-01), Miyanaga
patent: 5998292 (1999-12-01), Black et al.
patent: 0 698 288 (1996-02-01), None
patent: 0757431A2 (1997-02-01), None
patent: WO 92/03848 (1992-03-01), None
patent: WO 94/09513 (1994-04-01), None
patent: WO 94/25981 (1994-11-01), None
patent: WO 96/21943 (1996-07-01), None
patent: WO 97/45856 (1997-12-01), None
patent: WO 97/45862 (1997-12-01), None
IPEC Precision brochure for PACEJET II (© 1996), 2 pages.
Siniaguine, O., et al., “Plasma Processing of Silicon Wafers at Atmospheric Pressure”,Electronic Industry, Jun. 1994, pp. 27-30.
Siniaguine, Oleg, “Plasma Jet Etching at Atmospheric Pressure for Semiconductor Production”, First Int'l Symposium on Plasma Process-Induced Damage, May 13-14, 1996, Santa Clara, CA, pp. 151-153.
AZ Corporation, “Plasma Jet Etching Technology and Equipment; Silicon Wafer Thinning & Isotropical Etching at Atmospheric Pressure”, Semicon/Europe, Apr. 1995, Geneva, Switzerland, 4 pages.
Christensen, C., et al., “Wafer Through-Hole Interconnections with High Vertical Wiring Densities”,IEEE Trans. on Comp., Pkg,&Mfg. Tech, Part A, vol. 19, No. 4, Dec. 1996, pp. 516-521.
Anthony, T., “Forming Feedthroughs in Laser-Drilled Holes in Semiconductor Wafers by Double-Sided Sputtering”,IEEE Trans. on Comp., Hybrids,&Mfg. Tech, vol. CHMT-5, No. 1, Mar. 1982, pp. 171-180.

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