Electrical computers and digital processing systems: processing – Processing architecture – Distributed processing system
Reexamination Certificate
1998-05-27
2001-02-13
Donaghue, Larry D. (Department: 2783)
Electrical computers and digital processing systems: processing
Processing architecture
Distributed processing system
C712S004000
Reexamination Certificate
active
06189094
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of data processing. More particularly, this invention relates to data processing systems having a register bank and supporting vector operations.
2. Description of the Prior Art
It is known to provide data processing systems having a register bank and supporting vector operations. Examples of such systems are the Cray
1
and Digital Equipment Corporation MultiTitan processors.
The Cray
1
processor has separate vector and scalar register banks. If the opcode of the instruction being executed indicates a vector operation, then a sequence of data values are returned from the vector register bank in dependence upon a length value stored in a length register and a mask stored in a mask register. The length specifies how many data values are in the sequence and mask specifies which data values are returned from among a plurality of data values associated with the vector register indicated in the instruction.
The MultiTitan processor has a single register bank the registers of which can act serve either as scalars or vectors. The instruction itself includes flags that indicate whether a register specified is a scalar or a vector and a length field indicating the number of data values within the sequence when a vector register is used.
Vector instructions themselves are desirable as they allow code density to be increased since a single instruction can specify a plurality of data processing operations. Digital signal processing such as audio or graphics processing is particularly well suited to exploiting vector operations as there is often a requirement to perform the same operation upon a sequence of related data values, e.g. performing a filter operation by multiply a sequence of signal values by tap coefficients of a digital filter.
It is also desirable to perform data processing operations as quickly and efficiently as possible. One way of helping to increase speed and efficiency is to avoid having to reload or reposition data values that have already been stored within the register bank. A problem in achieving this is that instruction code that is able to reuse data values directly tends to be longer and more complex. If more instructions are needed to specify the operation required then this tends to slow down the processing and negate the purpose of seeking to reuse the data values within the register bank.
As an alternative to the use of general purpose processors such as the Cray
1
and MultiTitan processors, special purpose digital signal processing circuits are often provided with the specific role of supporting a small number of digital signal processing operations. Within these special purpose digital signal processing circuits, a common technique is to store the data values required within a large memory and then fetch the data values required for each manipulation as needed. The data values need not be reloaded or reposition within the large memory as the order and sequencing of their use is controlled by manipulation of the addresses used to access the large memory. A problem with this approach is that the circuits have to be specifically designed to match the operation being performed and so lack the flexibility and ease of integration with other functions that is provided by the use of a more typical general purpose processor.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide efficient and fast data processing whilst maintaining the flexibility of a general purpose processor using a register bank and instruction decoder supporting vector operations.
Viewed from one aspect the present invention provides an apparatus for processing data, said apparatus comprising:
a register bank having a plurality of registers; and
an instruction decoder responsive to at least one data processing instruction specifying a vector operation that executes a data processing operation a plurality of times using data values from a sequence of registers within said register bank; wherein
said register bank includes at least one subset of registers, said sequence of registers being within said subset; and
said instruction decoder controls said sequence of registers to wrap within said subset of registers.
Providing register wrapping within a subset (i.e. less than all) of the registers of the register bank allows compact code to be written that reuses data values within the register bank without requiring reloading or moving of the data values. The instruction codes for each use can start at different points within the subset and so act upon the data values in a different order with the hardware taking care of the wrapping needed without having to provide extra instructions to split the vector sequence. Furthermore, performing a vector operation upon a subset of registers that wrap upon themselves allows for the possibility to concurrently perform data transfers upon data values within registers not within the subset. The register wrapping can also be thought of as providing hardware support for a ring (circular) buffer type arrangement where, for example, data is loaded in and multiplied out of the buffer at point that chase each other round and round the buffer.
Whilst it is possible to have only a single subset of wrapping registers, it is advantageous to provide systems in which said vector operation executes said data processing operation using a plurality of respective data values from a corresponding plurality of sequences of registers;
said register bank contains a plurality of subsets of registers, said plurality of sequences of registers being within respective subsets; and
said instruction decoder controls said plurality of sequences of registers to wrap within respective subsets of registers.
Within digital signal processing operations it is often required to reuse the data values from two sequences (e.g. a FIR operation with taps and signal values to be multiplied and accumulated at different offsets or a matrix operation) and so multiple subsets of wrapping registers are desirable.
Whilst it is possible for the subsets to overlap, in practice the data values that require reuse in such situations are usually quite separate and so the subsets may be made disjoint. This makes the hardware implementation advantageously less complex.
It will be appreciated that the subsets could be formed of registers from positions intermixed with registers not within the subsets. However, programming and implementation are made easier when the subsets are a range of consecutively numbered registers.
The ranges could be spaced apart within the register bank, but in preferred embodiments the ranges are contiguous as this makes more efficient use of the register space available.
The ability of the invention to more effectively use vector operations is complemented in preferred embodiments which further comprise a memory and a transfer controller for controlling transfers of data values between said memory and registers within said register bank, said transfer controller being responsive to multiple transfer instructions to transfer a sequence of data values between said memory and a sequence of registers within said register bank.
The ability to transfer data values to and form blocks of registers within the register bank is well matched to the ability of the invention to efficiently use vector operations as it allows a block of registers to be reused several times and then swapped out with a single instruction.
The use of a sequence of registers in the vector operation and the division of the register bank into predefined subsets of registers may be efficiently implemented in preferred embodiments in which each range is addressed via an incrementer that wraps between the end points of that range.
The sequence of registers used in the vector operation could take many forms, e.g. every alternate register within the subset, however the most commonly useful situation is the one in which the sequence is a sequence of consecutive registers.
The above techniques can be used in any proces
Hinds Christopher Neal
Jaggar David Vivian
Matheny David Terrence
Seal David James
ARM Limited
Donaghue Larry D.
Nixon & Vanderhye P.C.
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