Digital-to-analog converter employing binary-weighted...

Details Digital-to-analog converter employing binary-weighted... Digital-to-analog converter employing binary-weighted...

1999-11-24

2001-11-13

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

C341S145000

Reexamination Certificate

active

06317069

ABSTRACT:

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
N/A
FIELD OF THE INVENTION
This invention relates generally to digital-to-analog converters and, more particularly, to digital-to-analog converters incorporating binary-weighted resistor arrays or ladders.
BACKGROUND OF THE INVENTION
A variety of circuits for the conversion of a digital word into an analog voltage are known. A digital-to-analog converter (DAC) typically employs a constant impedance resistor string or a binary-weighted resistor array to accomplish the conversion. A constant impedance resistor string is comprised of 2
N
series-connected resistors, where N equals the number of bit of the digital word to be converted. A voltage reference is placed across the string to thereby generate a series of monotonically increasing voltages. The value of the digital word determines which one of these voltages is selected as the analog output.
Binary-weighted resistor arrays require fewer resistors for a specified number of bits (2N versus 2
N
) and one common array is the “R-2R” ladder
10
illustrated in FIG.
1
. The R-2R ladder is comprised of a “runner” of series-connected resistors
2
, each having a resistance of R ohms, and a, plurality of “rungs,” one for each binary bit of the digital word. A rung includes a resistor
4
of 2R ohms and a switch
6
that is controlled by its associated binary bit signal. A voltage reference, V
ref
, is placed across the R-2R ladder producing binary-weighted currents that are typically summed and converted into an output voltage by an operational amplifier
8
.
Unlike the constant impedance resistor string, a binary-weighted resistor array is not an inherently monotonic structure wherein the analog output voltage is guaranteed to monotonically increase as the value of the digital word increases. To avoid the output noise caused by non-monotonic performance, the array resistors must be tightly matched. For example, the resistor matching for the i
th
bit of an n-bit converter should be within R/(2
n−i
) ohms.
Both the constant impedance resistor string, due to the large number of resistors required, and the binary-weighted array, due to the difficulty in matching the array resistors, are effectively limited in the number of bits that they can convert. To convert digital words having a large number of binary bits, some digital-to-analog converters divide the digital word into a most significant bit (MSB) segment and a least significant bit (LSB) segment and process each segment separately. A segmented DAC structure, described in U.S. Pat. No. 5,648,780, is illustrated in
FIG. 2. A
first divider stage
20
is responsive to the MSB segment and employs a constant impedance resistor string
22
to generate a series of reference voltages. A decoder
26
generates a plurality of switch control signals
27
to control the switch pairs of a switch string
24
and thereby select, based on the binary value of the MSB segment, an upper-level voltage reference and lower-level voltage reference appearing at a pair of output nodes
28
,
29
.
A second, last divider stage
30
employs a binary-weighted resistor ladder
32
to produce a voltage at an output node
38
. The output voltage depends upon both the established voltage reference range placed across the ladder
32
and the binary value of the LSB segment which controls a plurality of switches
34
. If the digital word to be converted is very large, one or more additional divider stages (not shown) may be placed between the first and last divider stages for the bits of the intermediate segments of the digital word.
To achieve the smallest possible package size, a DAC is commonly implemented as a monolithic integrated circuit. Typically, metal oxide semiconductor field effect transistor (MOSFET) devices are used for switches and diffused or implanted structures are used for the resistors. Unfortunately, a monolithic DAC still tends to be relatively large because the switch and resistive devices consume a significant amount of die space. The continued miniaturization of electronic equipment has resulted in a need for an even more compact monolithic DAC.
BRIEF SUMMARY OF THE INVENTION
In accordance with the invention, a monolithic digital-to-analog converter (DAC) is comprised of a binary-weighted array that uses a single n-type or p-type metal oxide semiconductor (MOS) device for each of the resistor/switch combinations that typically make up such arrays. Because a MOS device has a relatively high equivalent resistance per unit area and, furthermore, because the switching function is inherent in a MOS device, a much more compact layout can be achieved by using a single MOS device for each resistor/switch combination.
More particularly, the binary-weighted array has an “M-2M” ladder structure, where “M” refers to the effective resistance of a MOS device when enabled. The M-2M ladder includes one “2M” ladder “rung” for each binary bit, and each rung includes a complementary pair of upper and lower MOS devices series-connected at a common node. Each complementary MOS device has an effective resistance of 2M ohms when enabled and only one device in the pair is enabled at any given time depending upon the value of the associated binary bit. The rungs are connected in parallel and a voltage reference is placed across the pairs.
Permanently enabled MOS devices serve as resistors that interconnect the common nodes of adjacent LSB binary bit device pairs. These interconnecting MOS devices make up the “M” ladder “runner” and each has an effective resistance of M ohms. The voltage generated at the common node of the most significant bit is the analog output, which is isolated from the DAC output terminal by a unity gain buffer amplifier.
To handle digital words having a large number of bits, the DAC may segment the word into a MSB segment and LSB segment and also include an inherently monotonic resistor string. A series of incremental voltages are developed across the string and the binary bits of the MSB segment are used to select an upper-limit voltage reference and lower-limit voltage reference for the “M-2M” array. Because the upper and lower voltage references are limited to a relatively narrow range, the non-linear effects of a MOS device are largely avoided in the “M-2M” array.


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