Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Phase shift by less than period of input
Reissue Patent
2000-09-01
2001-11-20
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Phase shift by less than period of input
C327S238000, C327S254000, C327S344000
Reissue Patent
active
RE037452
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to phase shifting circuits and more particularly to a phase shifting circuit that may be used in quadrature clock generator for
for
providing quadrature output signals.
BACKGROUND OF THE INVENTION
A quadrature clock generator may be used in a delay locked loop (DLL) to provide two clock signals that are 90 degrees out of phase with one another. Typically, a first output clock signal (the “I” output clock signal) is in phase with the input reference clock signal, and a second output clock signal (the quadrature or “Q” output clock signal) is 90 degrees out of phase with the input reference clock signal. Both output clock signals of the quadrature clock generator have the reference frequency. The output clock signals are phase mixed to provide a desired phase difference or delay between the output clock signal of the DLL and the input reference clock.
Cyclic variations from the desired phase difference between the output clock signals of the quadrature clock generator result in “jitter.” For DLL purposes, the jitter of the quadrature clock generator affects the timing margins of the DLL, increasing lock acquisition time for the DLL. Therefore, reduced jitter is desirable.
According to one prior art method, a quadrature clock generator first divides the frequency of the input reference clock signal by two and then operates on the reduced frequency signal to produce two clock signals that are 90 degrees out of phase with one another. A DLL using a frequency dividing quadrature clock generator then must double the frequency of the clock signals to produce the desired output clock signals of the original frequency.
According to an alternative prior art method, a quadrature clock generator operates “at frequency” to provide quadrature clock signals without the intermediate steps of frequency dividing and doubling. A fixed delay element is typically used to provide the desired phase relationship. When compared to frequency dividing quadrature clock generators, at frequency quadrature clock generators have the advantages of reduced circuit complexity, reduced die area, and reduced power consumption.
Generally, frequency dividing quadrature clock generators are able to maintain the desired phase relationship between the output clock signals over a wider range of input reference clock frequencies than at frequency quadrature clock generators. Furthermore, when compared to at frequency quadrature clock generators, frequency dividing quadrature clock generators are better able to maintain the desired phase relationship in view of process variations, supply variations, and temperature variations.
Wherein frequency dividing quadrature clock generators are capable of providing adequate jitter performance, a DLL that uses a frequency dividing quadrature clock generators may exhibit bi-modal jitter (and therefore worse timing margins) due to the mismatching of components used in the frequency doubling. Thus, the components of frequency dividing quadrature clock generator must be closely matched to reduce jitter, further increasing the cost of manufacturing a frequency dividing quadrature clock generator.
SUMMARY AND OBJECTS OF THE INVENTION
Therefore, an object of the invention is to provide an at frequency quadrature clock generator having improved jitter performance.
These and other objects are provided by a quadrature clock generator that includes an at frequency phase shifting circuit for providing the Q output clock signal and a first comparator for providing the I output clock signal. Both the phase shifting circuit and the second comparator are coupled to receive an input reference clock signal. The phase shifting circuit comprises a triangle wave generator coupled in series with a second comparator. The triangle wave generator outputs a pair of complementary triangle wave signals in response to the input reference signal. The second comparator outputs the Q output clock signal in response to a comparison between the pair of complementary triangle wave signals. To better ensure that the output clock signals of the first comparator and the phase shifting circuit are in quadrature, the first and second comparators are matched such that the propagation delays associated with the comparators are equal.
According to alternative embodiments, the phase shifting circuit may be used alone to provide a predetermined fixed delay. Further, the quadrature clock generator may be used as a component of a DLL.
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Chau Pak Shing
Donnelly Kevin S.
Rambus Inc.
Shemwell Charles E.
Tran Toan
LandOfFree
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