Electrical transmission or interconnection systems – Plural load circuit systems – Control of current or power
Reexamination Certificate
1999-10-13
2001-02-20
Jackson, Stephen W. (Department: 2836)
Electrical transmission or interconnection systems
Plural load circuit systems
Control of current or power
Reexamination Certificate
active
06191499
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to power regulation and in particular to multiple processor machines. Still more particularly, the present invention relates to a voltage regulation system, method of operation and multiple processor apparatus employing the system or method.
2. Description of the Related Art
With the proliferation of small computers and the extension of their use into more powerful applications and network-centric computing environments, the performance requirements for these computing machines are increasing to ever higher levels. Consequently, the application of multiple processors, or N-way processors, are increasingly being applied in lower-end, i.e., lower cost, machines.
As processor performance has increased, voltage levels used to power these processors has correspondingly decreased. Additionally, as input voltage levels have decreased, input current has increased along with dynamic current effects needed to support higher speed operation of these processors. This has necessitated the need for “point of load” voltage regulation that is implemented in close proximity to the processor. To provide for this point of load voltage regulation, small Voltage Regulator Modules (VRMs) are becoming standard devices and are presently employed to power these new low voltage processors.
Currently, in multiple processor, or N-way processor machines, each processor is typically powered by two paralleled VRMs. Additionally, in certain custom designs, a bank of processors is powered by a N+1 (where N is the minimum number of regulator required to run the processor bank) bank of regulator engines. In both cases, redundancy in the VRMs is utilized to keep all the processors in operation in the event of a failure in the voltage regulation stage that is powering the processor or processors. Both of the above-described redundant systems, i.e., parallel and N+1, however, are not 100% fault tolerant. There are certain failure modes, e.g., a short circuit condition in a processor supported by the VRMs, that may shut down the entire system. This lack of robustness permits a failure in a single processor to take down the entire multiple processor machines.
Furthermore, with lower-end multiple processor machines, cost considerations are of paramount importance. The implementation of redundant systems, as described above, invariably increases the cost of multiple processor machines. For example, in a dual redundant system wherein two VRMs are used to power a single processor, the cost of the multiple processor machine attributable to the VRMs are doubled. Similarly, employing a N+1 bank of regulator engines also raises the cost and complexity of a multiple processor machine due to the added regulator, along with the complex monitoring and switching circuitry that must be employed to ensure that all the processors are in operation.
Accordingly, what is needed in the art is an improved voltage regulation system that mitigates the above-described limitations and, more particularly, a voltage regulation system that is more robust and cost effective to implement in a multiple processor machine.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an improved voltage regulation system, method of operation and a multiple processor apparatus employing the system or method.
To achieve the foregoing object, and in accordance with the invention as embodied and broadly described herein, a voltage regulation system for use with a multiple processor apparatus is disclosed. The voltage regulation system includes a plurality of voltage regulation modules (VRMs) coupled to a plurality of processors, each one of the VRMs is dedicated to only one of the plurality of processors wherein a processor is powered down in response to a failure of its respective dedicated VRM.
In one embodiment of the present invention the number of processors and number of VRMs utilized are equal. In a related embodiment, the multiple processor apparatus is a N-way processor.
In yet another embodiment of the present invention, each pair of processor and dedicated VRM defines a separate power domain. In an advantageous embodiment, each pair of processor and dedicated VRM is located on a separate circuit card. This arrangement electrically isolates each pair of processor and VRM from each other, thus preventing failures in one pair from affecting the others.
In another embodiment of the present invention, the plurality of VRMs are coupled to a power converter that, in an advantageous embodiment, is a DC—DC converter. It should be apparent to those skilled in the art that the type of power converter employed is dependent on the nature of the external power source that is available. Consequently, if the external power source provides an AC voltage, the power converter may be a rectifier.
The foregoing description has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject matter of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
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La Rocca Paul Jeffrey
Severson Paul Steven
Smid Jan Douglas
Zamzow Steven Brian
Felsman Bradley Vaden Gunter & Dillon, LLP
International Business Machines - Corporation
Jackson Stephen W.
Polk Sharon
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