Photography – Fluid-treating apparatus – Heating – cooling – or temperature detecting
Reexamination Certificate
2001-04-11
2001-11-20
Rutledge, D (Department: 2851)
Photography
Fluid-treating apparatus
Heating, cooling, or temperature detecting
C396S611000, C396S626000
Reexamination Certificate
active
06318913
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to a method and apparatus for manufacturing a semiconductor integrated circuit (“IC”). More specifically, this invention relates to an improved method and apparatus for the dispensing of a plurality of allocations of a photoresist developer while maintaining an improved temperature profile.
DESCRIPTION OF THE PRIOR ART
The present invention applies particularly to the fabrication of semiconductor integrated circuits. Some examples of these semiconductor integrated circuits comprise non-volatile memory integrated circuits. Non-volatile memory integrated circuits include an EPROM, an EEPROM, a flash memory device, and a complementary metal oxide silicon (“CMOS”) type device. Exemplary devices may comprise field-effect transistors (“FET”) containing a metal gate over thermal oxide over silicon (“MOSFET”), as well as other ultra-large-scale integrated-circuit (“ULSI”) systems.
Integrated circuits are utilized in a wide variety of commercial and military electronic devices, including, e.g., hand held telephones, radios and digital cameras. The market for these electronic devices continues to-demand devices with a lower voltage, a lower power consumption and a decreased chip size. Also, the demand for greater functionality is driving the “design rule” lower, for example, into the sub-half micron range. The sub-half micron range may comprise, e.g., decreasing from a 0.35-0.25 micron technology to a 0.18 micron or a 0.15 micron technology, or even lower.
These integrated circuit devices are generally fabricated in groups on a semiconductor wafer. A portion of this fabrication involves utilizing a photolithography process to pattern the semiconductor wafer. This photolithography process is conventionally utilized in a semiconductor wafer production.
Specifically, in a portion of the photolithography of these wafers, a photoresist coater and developer system is utilized in the patterning of various layers of the wafer that will form the circuit device. The photoresist coater and developer system applies, or coats, a light-sensitive resin, i.e., a photoresist layer, to wafers by depositing a pre-selected amount of the photoresist solution. Next, the system spins the wafers at a relatively high rate of speed to distribute the photoresist into a relatively even coating over the wafer. Then, the wafers are baked to induce a volatilization of a casting solvent in the photoresist. Next, the wafers are exposed to a light source, e.g., a deep ultraviolet (“DUV”) light source, for patterning. The wafers are baked and then developed by a chemical treatment, and are again baked to dry the wafers.
Conventional examples of resist coater and developer systems, e.g., are the Tokyo Electron Limited (TEL) sub-half micron compatible Coater/Developer Clean Track systems. Conventional systems include systems that utilize a chemically amplified resist (“CAR”) in the deep ultraviolet (“DUV”) process that has been adopted for the sub-half micron design rule type of circuit devices.
As to the development of the photoresist that has been formed on the wafer, conventionally, a chemical developer is utilized to remove areas defined in the steps of masking and exposure of the photoresist layer, that has been deposited on the wafer. The development of the photoresist is an important part of the wafer fabrication.
For example, in sub-half micron semiconductor processing, one of the most important parameters in the photolithography area is the critical dimension (“CD”). The above described relatively complex integrated circuits will only function as designed if the critical dimensions are within specification. There are many parameters that control the critical dimension. One of these parameters comprises the temperature of the photoresist chemical developer solution when the wafer is being developed.
FIG. 1
illustrates a conventional photoresist chemical developer solution dispensing apparatus, or nozzle assembly
10
. The nozzle assembly
10
includes a nozzle unit
30
that is connected to a nozzle cap
40
by utilizing fastening devices, e.g., nuts and bolts, that are not shown. The fastening devices first pass through the fastening holes
24
, starting from a lower surface of the nut plate
22
, then through the fastening holes
34
of the nozzle unit
30
, and finally through the fastening holes
44
of the nozzle cap
40
. In order to seal the nozzle assembly
10
, an O ring
60
is provided between the nozzle cap
40
and a top interior recessed groove
31
of the nozzle unit
30
.
Although not shown, a plurality of nozzle ports
28
for dispensing a chemical developer solution are located on a lower portion or underside of the nozzle unit
30
. The chemical developer is introduced into the nozzle assembly
10
through one or more input ports
46
of the nozzle cap
40
.
A temperature control unit
300
, that includes a heating coil comprising a single ⅜ inch diameter heat exchanger tube
302
, is centrally placed within the nozzle unit interior
38
. This heat exchanger tube
302
carries a temperature control liquid within an interior sealed portion of this heat exchanger tube
302
. Suitable temperature control unit input and output ports
304
,
306
, are respectively provided to transport the temperature controlled fluid into the interior sealed portion of the heat exchanger tube
302
. The conventional temperature control liquid then achieves a thermal equilibrium with the allocation of chemical developer that has just been introduced, via the input ports
46
, into the nozzle unit interior
38
of the nozzle unit
30
. Also provided is an air bleed port
46
A that is routed to a drain and may be utilized when introducing the developer.
By providing this close physical association between the temperature control unit and the chemical developer nozzle ports
28
, a relatively strict or precise temperature control of a single developer allocation is achieved. For example, the developer may be supplied to the nozzle unit interior
38
at a temperature that is approximately 2-5° C. different, e.g., lower, than the desired control temperature, e.g., of approximately 23° C. Also, the developer may be supplied to the nozzle unit interior
38
at a greater than 5° C. temperature difference than the desired control temperature. The temperature control of the chemical developer solution is provided until it is dispensed or deposited by the nozzle ports
28
onto the wafer
220
, as is shown in
FIGS. 2A-B
.
In
FIG. 2A
, a conventional photoresist coating and developing system is shown.
FIGS. 2A-B
illustrate a technique that is conventionally referred to as a puddle procedure.
Specifically, the puddle process comprises the following technique that is illustrated by a conventional single wafer spray unit. In
FIG. 2A
, the semiconductor wafer
220
is held upon a rotatable table or track chuck
200
. First, the wafer
220
is spun utilizing the chuck
200
. A first allocation of the photoresist developer
235
is dispensed through the nozzle ports
28
to an upper surface of the wafer
220
that further comprises a photoresist layer
234
that has been patterned and exposed by light. While the temperature controlled chemical developer
235
is being dispensed, the wafer
220
is spun at a relatively low number of revolutions per minute (“RPM”). The chemical developer
235
is now utilized to cure the photoresist.
The spinning of the wafer
220
is then stopped, as shown in FIG.
2
B. The first allocation of the chemical developer
235
has been deposited by the nozzle ports
28
so as to cover the photoresist upper surface. Surface tension now holds the developer
235
on the wafer
220
so as to form a puddle
237
. The puddle
237
of developer
235
then sits upon the surface of the wafer
220
for a specified or required period of time. For example, a specified sit time of 23 seconds may be utilized. Thus, in essence, this puddle technique provides for a single wafer topside-only immersion process.
When the specified sit time has ex
Kent Eric
Marinaro Vincent L.
Wakamiya Ted
Advanced Micro Devices , Inc.
Foley & Lardner
Rutledge D
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