Pulse or digital communications – Equalizers
Reexamination Certificate
1999-12-13
2001-11-06
Bocure, Tesfaldet (Department: 2631)
Pulse or digital communications
Equalizers
Reexamination Certificate
active
06314132
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of digital signal processing and, more particularly, to a microprocessor structure and a method for implementing digital filter operations.
2. Description of Related Art
The finite impulse response filter (FIR) and inner product are known as the fundamental operation blocks of a digital signal processor (DSP). The FIR operation is provided to process the following equation:
y
n
=
∑
i
=
0
N
-
1
c
i
x
n
-
i
,
wherein, N is the order of a filter, x
n
is the nth input, y
n
is the nth output, c
i
(i=0 . . . N−1) is the constant coefficient of the filter. Taking N=4 as an example, we have:
y
n
=c
0
x
n
+c
1
x
n−1
+c
2
x
n−2
+c
3
x
n−3
,
while the operation of the next data is:
y
n−1
=c
0
x
n+1
+c
1
x
n
+c
2
x
n−1
+c
3
x
n−2
.
To perform proper operations on each input value in a conventional digital signal processor, the oldest data is overwritten by the next data, and the pointers of the DSP will be moved to the newest data. The positions of the pointers are automatically calculated during the operation. Referring to
FIG. 3A
, before performing an operation to a first value, the arrangement of the memory is of . . . c
0
, c
1
, c
3
, x
n
, x
n−1
, x
n−2
, x
n
. . . , wherein pointer R
1
and pointer R
2
are respectively pointed to C
O
and x
n
. Referring to
FIG. 3B
, before the next operation is performed, the X
n+1
, is overwritten by the x
n+1
, and the pointer R
2
is pointed to x
n+1
. When performing the required multiplication operations for N times to each value, an additional address generator
31
is provided to generate a new pointer Rn to perform the multiplication/addition operation for each time. Such operation is performed by the following equation:
R
2
=(R
2
−Base+i)% N+Base,
wherein, N=4, i=0 . . . N-1, “Base” is a base address in which the x is stored, and R
2
is the address of a first data being processed by the current operation.
Accordingly, it is known that the conventional digital signal processor must be provided with additional hardware to perform the operation of updating the content of the pointer for carrying out a multiplication operation during each operation cycle. While performing such operation, three addition/subtraction operations and one modulo operation must be executed, which result in a relatively high hardware cost. Moreover, a microprocessor usually does not have a hardware multiplier so it cannot efficiently provide the operation functions of such kind of digital signal processing. Therefore, considering the hardware cost, there is a need to have a microprocessor which can efficiently implement digital filter operations.
BRIEF SUMMARY OF THE INVENTION
One object of the present invention is to provide a microprocessor structure with simple hardware resources for implementing digital filter as well as inner product operations.
Another aspect of the present invention is to provide a method for implementing digital filter operations by means of a microprocessor to effectively accomplish the digital filter operations.
In accordance with one aspect of the present invention, there is provided a microprocessor structure for implementing digital filter operations performed on a memory sequentially storing multiple digital filter coefficients and input values to be filtered. The microprocessor structure includes: a register set including a first register having a value pointed to a digital filter coefficient of the memory, and a second register having a value pointed to an input value of the memory; an accumulator circuit for reading the digital filter coefficient pointed by the value of the first register and the input value pointed by the value of the second register, the accumulator circuit multiplying the digital filter coefficient by the input value using an arithmetic logic unit to obtain a product, and the product being accumulated; and, an increment/decrement unit for performing increment/decrement operations to the first register and the second register. By such an arrangement, when the accumulator circuit performs an accumulation operation, the input value read by the accumulator circuit is temporarily stored, and the increment/decrement unit respectively increases/decreases the values of the first register and the second register and the values are stored back to the first register and the second register. The accumulator circuit takes the increased/decreased values in the first register and the second register as addresses to respectively read a digital filter coefficient and an input value from the memory, and takes the increased/decreased values in the second register as an address to write the temporarily stored input value into the memory, and then proceeding a next operation.
In accordance with another aspect of the present invention, there is provided a method for implementing digital filter operations performed on a memory by using a microprocessor. The memory sequentially stores multiple digital filter coefficients and input values to be filtered. The method includes the steps of: (A) reading a digital filter coefficient and an input value; (B) performing a multiplication operation to said digital filter coefficient and said input value to obtain a product, said product being accumulated; (C) retaining said input value; (D) reading a next digital filter coefficient and a next input value; and (E) moving the retained input value to a memory location provided for storing the next input value, and returning to step (B) to repeatedly execute the steps until the product of a last digital filter coefficient and a last input value is accumulated.
Further benefits and advantages of the present invention will become apparent after a careful reading of the detailed description with appropriate reference to the accompanying drawings.
REFERENCES:
patent: 3573624 (1971-04-01), Hartmann
patent: 4386430 (1983-05-01), Treiber
patent: 5461641 (1995-10-01), Abbiate et al.
Lee Hwan-Rei
Liu Te-Chung
Shih Daniel
Bacon & Thomas
Bocure Tesfaldet
Sunplus Technology Co. Ltd.
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