Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-02-28
2001-10-16
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185210, C365S185290
Reexamination Certificate
active
06304487
ABSTRACT:
FIELD OF THE INVENTION
The present invention is directed to an apparatus and method to program or erase a memory cell.
RELATED ART
FIG. 1
illustrates a cross sectional view of a conventional memory transistor, also known as a memory cell. The memory transistor includes a control gate CG, a floating gate FG, a drain D, a source S, and a well W. Thin oxide layers isolate the floating gate FG from the control gate CG as well as the well W.
FIG. 2
schematically illustrates a conventional NAND type flash memory array
100
that includes numerous memory cells, each depicted in
FIG. 1. A
“string” includes a selection transistor T
i−1
, memory transistors M
i−1
to M
i−j
, and a selection transistor T
i−2
, all being serially coupled. Each string can be coupled to a bit line BLj and a common source CS through selection transistors T
i−1
and T
i−2
, respectively. The control gates for selection transistors T
i−1
and T
i−2
are respectively connected to selection lines Sl
1
and Sl
2
. The control gates for the memory transistors M
i−1
to M
i−j
are respectively connected to word lines W
1
to W
j
. Typically, a read operation is performed on a page basis, i.e., flash memory cells coupled to a word line are read together.
Herein, a memory transistor represents logical LOW when it is programmed to have a threshold voltage that is larger than a predetermined minimum threshold voltage for logical LOW bits. Correspondingly, a memory transistor represents a logical HIGH when it is erased to have a threshold voltage that is less than a predetermined maximum threshold voltage for logical HIGH bits. One skilled in the art will understand that logic level assignments to the predetermined minimum and maximum threshold voltages are arbitrary.
A large variation in the programming and erasing characteristics of individual NAND type flash memory transistors among a memory array is common. The variations can be due to structural differences, which cause difference in threshold voltage characteristics. Such variations introduce differences in programming and erasing speeds among memory transistors. Conventional NAND type flash memory arrays use fixed programming and erase voltages that cannot adjust to programming and erasing characteristics of the memory transistors. Some memory transistors in flash memory arrays do not respond to the fixed programming and erase voltages of NAND type flash memory arrays. Accordingly, NAND type flash memory arrays that include an intolerably high number of non-responsive memory cells are typically discarded. As such, the yield of usable NAND memory arrays fluctuates. Low yield increases the manufacturing cost of NAND memory, and hence leads to a less profitable and less competitive position.
Thus what is needed is a method and apparatus to adaptively control the programming and erase voltages of NAND type flash memory and thereby increase the proportion of usable memory cells.
SUMMARY
In accordance with one embodiment of this invention, a voltage control circuit that programs a memory cell comprises a register device and a voltage output circuit. The register device is selectively coupled to a source of programming voltage value to receive a programming voltage value. The voltage output circuit is coupled to the register device to receive the programming voltage value and to output a corresponding programming voltage to the memory cell. In one implementation of this embodiment, the control circuit further comprises a verify circuit and a voltage storage circuit. The verify circuit signals a time the memory cell is successfully programmed and the voltage storage circuit stores the programming voltage value if the time to successfully program the memory cell is acceptable. Thus, various programming voltage values can be applied to the memory cell using the source, the register, and the voltage output circuit. The time to successfully program the memory cell for each programming voltage value can be determined from the verify circuit. From these times, an optimal programming voltage value can be determined and stored in the voltage storage circuit.
In accordance with another embodiment of this invention, a method for programming a memory cell comprises storing a programming voltage value, retrieving the stored program voltage value, converting the retrieved program voltage value into a voltage signal, and applying the voltage signal to the memory cell. In one implementation of this embodiment, the method further comprises determining if the program voltage value produces a suitable programming speed and storing the program voltage value if it produces a suitable programming speed.
In accordance with one embodiment of this invention, a voltage control circuit that erases a memory cell comprises a register device and a voltage output circuit. The register device is selectively coupled to a source of erase voltage value to receive an erase voltage value. The voltage output circuit is coupled to the register device to receive the erase voltage value and to output a corresponding erase voltage to the memory cell. In one implementation of this embodiment, the control circuit further comprises a verify circuit and a voltage storage circuit. The verify circuit signals a time the memory cell is successfully erased and the voltage storage circuit stores the erase voltage value if the time to successfully erase the memory cell is acceptable. Thus, various erase voltage values can be applied to the memory using the source, the register, and the voltage output circuit. The time to successfully program the memory cell for each erase voltage value can be determined from the verify circuit. From these times, an optimal erase voltage value can be determined and stored in the voltage storage circuit.
In accordance with another embodiment of this invention, a method for erasing a memory cell comprises storing an erase voltage value, retrieving the stored erase voltage value, converting the retrieved erase voltage value into a voltage signal, and applying the voltage signal to the memory cell. In one implementation of this embodiment, the method further comprises determining if the erase voltage value produces a suitable erase speed and storing the erase voltage value if it produces a suitable erase speed.
Various embodiments of the present invention will be more fully understood in light of the following detailed description taken together with the accompanying drawings.
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Chen Pau-Ling
Hong James M.
Le Binh Quang
Pawletko Joseph G.
Advanced Micro Devices , Inc.
Auduong Gene N.
Hsia David C.
Kwok Edward C.
Nelms David
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