Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2000-09-26
2001-11-20
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C451S041000
Reexamination Certificate
active
06319836
ABSTRACT:
FIELD
This invention relates to the field of integrated circuit processing. More particularly the invention relates to a method for planarizing layers of an integrated circuit.
BACKGROUND
There is continual pressure for integrated circuits to be increasingly faster and increasingly more powerful. Both of these objectives tend to be influenced by the size of the integrated circuits. By fabricating smaller integrated circuits, electrical pathways are shorter and more devices are formed within a given space, which tends to result in a faster, more powerful integrated circuit.
As the size of devices is reduced, it is increasingly difficult to adequately fill and cover the devices with the successive layers of material from which the devices are formed. This is because the small feature size tends to produce surfaces that are extremely uneven. If the extremely uneven surfaces are not modified in some manner, then the overlying layers of material tend to suffer from a variety of problems, such as not conforming to the underlying surface in a uniform manner, forming pinholes and cracks either during deposition or during subsequent processing, and cracking from unbalanced and unalleviated stresses.
These problems, and others, are reduced in large measure by planarizing in some manner an existing underlying surface of an integrated device after it is formed and before an overlying layer is deposited. One method of planarizing is chemical mechanical polishing. During chemical mechanical polishing, the face of the substrate in process is held against a rotating polishing pad by an end effector that contacts the back of the substrate. The end effector may also be rotating and translating the substrate over the surface of the polishing pad. Typically, a slurry of some sort, such as water, aqueous etchants, or a polishing rouge is present on the pad to aid in the polishing action.
As the abrasion between the substrate surface and the pad occurs, material is removed from the surface of the substrate. The material removed from the surface of the substrate is removed at a rate that is dependent upon several factors, such as the speed of the pad, the type of etchant or rouge that is used in the process, and the specific characteristics of the materials which comprise the surface being polished away in the chemical mechanical polishing process. Therefore, even with all other variables held constant, different types of materials tend to have different chemical mechanical polishing rates.
For example, if a surface that is being polished has regions of two different materials, one of the materials may have a polishing rate that is greater than the polishing rate of the other material. In this case, the regions of the surface that are formed of the material with the greater polishing rate will tend to erode at a faster rate than the regions that are formed of the material with the slower polishing rate. When this happens, the thickness of the surface decreases faster in the high polishing rate regions and the thickness of the surface decreases slower in the low polishing rate regions. This difference in the rate at which the thickness of the surface decreases tends to cause a surface defect at the interface between the regions with different polishing rates. This surface defect tends to resemble a taper at the interface between the higher polishing rate region and the lower polishing rate region, where the region with the lower polishing rate is at a higher level than the region with the higher polishing rate.
As the very purpose for performing the chemical mechanical polishing process is to reduce and planarize the topographical features of the surface being polished, the taper surface defect is viewed as a deleterious anomaly in the polished surface, and is not desired. However, the design goal of elimination of the deleterious taper is in competition with the design goal of forming surfaces that have regions formed of different materials, some of which may have different polishing rates.
What is needed, therefore, is a system for planarizing the surface of an integrated circuit that reduces or eliminates the deleterious taper that forms between regions of the surface that are formed of materials that have different polishing rates.
SUMMARY
The above and other needs are met by an improvement to a method for planarizing an integrated circuit. The integrated circuit is to be planarized to an upper surface using chemical mechanical polishing. The upper surface of the integrated circuit includes regions of a first material and regions of a second material. The first material has a first polishing rate and desired chemical, physical, and electrical properties. The second material has a second polishing rate and desired chemical, physical, and electrical properties. The first polishing rate is greater than the second polishing rate. The regions of the first material adjoin the regions of the second material at interfaces. The upper surface of the integrated circuit is overlaid with a top layer of the second material, that is to be removed by the chemical mechanical polishing. Both the regions of the second material and the top layer of the second material are deposited during a deposition. The upper surface of the integrated circuit tends to form deleterious tapers at the interfaces between the first material and the second material when the chemical mechanical polishing is taken past a desired end point.
The improvement comprises modifying the second material to increase the second polishing rate of the second material by adding a dopant to the second material prior to planarizing the integrated circuit. The dopant does not significantly adversely affect either the desired chemical, physical, and electrical properties of the second material, or the desired chemical, physical, and electrical properties of the first material.
Thus, by modifying the second polishing rate of the second material, the difference in polishing rates between the first material and the second material is reduced, and the deleterious tapers in the top surface, which are caused at least in part by over polishing a surface that has regions of different materials that have different polishing rates, tend to be eliminated or dramatically reduced, depending at least in part upon how closely the second polishing rate is matched to the first polishing rate by the modification of the second material.
In various preferred embodiments of the invention, the first material is monocrystalline silicon, the second material is silicon oxide, and the dopant is phosphorous. Modifying the silicon oxide in this manner preferably converts the silicon oxide to phosphosilicate glass. The dopant is preferably added to the second material to a concentration of between about 0.5 weight percent and about ten weight percent, and most preferably about three weight percent. In a most preferred embodiment, the dopant is added to the second material during the deposition of the second material, such as during a high density plasma deposition. Most preferably, the second polishing rate of the second material is modified to be substantially equal to the first polishing rate of the first material.
According to another aspect of the invention, an improved integrated circuit is provided on a monocrystalline silicon substrate. The improvement comprises isolation structures of phosphosilicate glass, where the monocrystalline silicon substrate has a first polishing rate and the phosphosilicate glass isolation structures have a second polishing rate, and the first polishing rate is substantially equal to the second polishing rate. Structures of other material, such as polysilicon or amorphous silicon are also comprehended.
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Dunton Samuel V.
Lee Ming-Yi
Hoang Quoc
LSI Logic Corporation
Luedeka Neely & Graham P.C.
Nelms David
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