Multiplex communications – Communication techniques for information carried in plural... – Combining or distributing information via time channels
Reexamination Certificate
1996-12-17
2001-11-13
Horabik, Michael (Department: 2735)
Multiplex communications
Communication techniques for information carried in plural...
Combining or distributing information via time channels
C370S350000, C370S514000, C375S365000
Reexamination Certificate
active
06317441
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to a slot receiving synchronous circuit, and more particularly to a slot receiving synchronous circuit for a digital mobile communication system provided in a communication apparatus such as a digital cellular phone, a digital cordless phone, or a satellite communication system employing time-division-multiple-access (TDMA) as its communication scheme.
DESCRIPTION OF THE RELATED ART
Digital mobile communications perform communication by defining a time frame which becomes the basic cycle for transmission and receiving of signals, and then by transmitting or receiving digital data signals using predetermined time intervals (e.g., “time slots”) assigned in the time frame.
Accordingly, because multiple channels can be multiplexed in the same carrier with this time slot, it is necessary to adjust the timing between systems performing communication, so that transmission signals being transmitted through individual channels do not overlap one another, and thereby do not interfere with each other.
Thus, to adjust the timing of each communication system performing transmission and receiving, the communication systems have a common time reference. A slot counter synchronizes the timing between systems.
Specifically, when the slot counter detects a signal with a specific bit pattern (e.g., a unique word or synchronous word), a count value is set as an initial value for synchronization. The count value contains time information of how long a time slot should take from the time the unique word is detected, so that synchronization with the other system is matched.
FIG. 3
shows a block diagram of a conventional slot synchronous circuit which includes an input control circuit
31
for receiving and controlling input data, and an m-bit receiving data shift register
32
having a length equal to the data length of a communication slot where m is preferably an integer greater than 2. Typically, there are 240 bits, with the bit cycle of the bit counter being 240 bits. The receiving data shift register
32
receives the input data (referred hereafter as “received” or “receiving” data) from the input control circuit
31
.
A k-bit unique word detector circuit
33
, independently input with the data output from the input control circuit
31
, detects a specific bit pattern (e.g., a unique word or synchronous word) from the data input thereto. A slot counter circuit
34
establishes slot synchronization with an output detection signal of the unique word detector circuit
33
. A timing control circuit
35
times an entire reception operation, and a bit counter circuit
36
establishes bit synchronization under the control of the timing control circuit
35
and provides an input to the slot counter circuit
34
at the end of each bit cycle. Also shown are a central processing unit (CPU)
37
for controlling the above-mentioned elements of the circuit through the timing control circuit
35
.
Hereinbelow, the operation of the conventional slot receiving synchronous circuit is described.
First, the received data is serially input into the receiving data shift register
32
through the input control circuit
31
. Simultaneously, the received data is serially input into the unique word detector circuit
33
and the receiving data shift register
32
. The received data is compared with a known unique word pattern of k bits (wherein k is less than m) stored in a register (illustrated in FIG.
4
and discussed below) within the unique word detector circuit
33
.
The unique word detector circuit
33
has a circuit configuration as shown in FIG.
4
. The receiving data is serially input into a D-input terminal of a D-type flip-flop
41
1
in the initial stage of a k-stage cascade-connected, D-type flip-flop
41
1
-
41
k
(where k is less than m). Bit values of receiving data are sequentially shifted to the D-type flip-flop in the next stage every time a clock is input.
Outputs of the D-type flip-flop
41
1
-
41
k
are also input into respective adders
42
1
-
42
k
, and the outputs are exclusively logically summed with each bit value of a known k-bit unique word pattern. For example, the unique word pattern is typically the same, for example, for all portable phones. The pattern is predetermined at the transmitter end and is output thereat. The adders
42
1
-
42
k
provide a value of logical “0” (e.g., low level) when both input values match, and provide a value of logical “1” (e.g., high level) when they do not match.
Each addition result output from the adders
42
1
-
42
k
is supplied to a logic circuit
44
. As discussed above, a logical “0” value (hereinafter also called a “matched signal”) is output only when the individual output values of the D-type flip-flop
41
1
-
41
k
match the k-bit unique word pattern from the unique word pattern register
43
for all bits. A logical “1” is output when at least one bit of the k-bit outputs of the D-type flip-flops
41
1
-
41
k
does not match the k-bit unique word pattern stored in the unique word pattern register
43
.
Referring to
FIG. 3
again, the slot counter circuit
34
is reset when the unique word detection signal is input. The slot counter circuit
34
establishes a “weak” synchronization as an initial value for synchronization. For purposes of this application, a “weak” synchronization is defined as using the output of the bit counter circuit as a “rough” value or “rough” approximation of synchronization. Thus, based on the bit counter circuit, the slot counter circuit
34
establishes a rough or general synchronization, not a precise synchronization.
Generally, there are two ways to achieve synchronization. First, the slot counter circuit is used to synchronize with the input of the reset signal. Secondly, the bit counter circuit is used to count clocks which roughly synchronize the system. However, when only the slot counter is reset (e.g., only the first method is performed) the bit counter circuit is still not synchronized with the transmission bit clock.
The slot counter circuit
34
informs the timing control circuit
35
of the establishment of the weak synchronization, and the bit counter circuit
36
is reset with the output of the timing control circuit
35
.
Since the bit counter circuit
36
counts up the bit clock with a rough m-bit value containing an error of several bits, receiving data in synchronization is possible only after a correction bit is defined by repeating the receiving operation several times, and by several normal receiving operations with the timing control circuit
35
. Thus, the “rough” m-bit error occurs, as described above, in conventional systems. Hence, the operation must be repeated unnecessarily several times, and thus several cycles lost.
Thus, the above-mentioned conventional slot receiving synchronous circuit has several drawbacks. Specifically, the conventional slot receiving synchronous circuit is required first to synchronize the slot because it detects the unique word by the unique word detector circuit
33
independently from the receiving data shift register
32
.
Here, although the receiving data latched at the detection timing of a unique word is temporarily stored in the receiving data shift register
32
, since the positional relationship is not synchronized between the unique word detection position and the receiving data in the shift register
32
, the receiving data “drifts” from a normal position, and is in a different position than where it should be. As a result, correcting the bit position for normalization becomes necessary, or discarding the receiving data at the time of unique word detection is required, so as to get the receiving data from the top (e.g., beginning or head) of the slot again.
Additionally, since to receive data correctly, the receiving data is again input into the receiving data shift register
32
from the beginning of the slot indicated by the slot timing, a time of at least one slot until the completion of receiving the data is required. Thus, an inefficient and time-consuming operation results.
Further
Harper Kevin C.
Horabik Michael
McGinn & Gibb PLLC
NEC Corporation
LandOfFree
Method and apparatus for synchronizing slot receiving data does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for synchronizing slot receiving data, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for synchronizing slot receiving data will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2602575