Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate plural instruction...
Reexamination Certificate
1997-10-03
2001-11-13
Chan, Eddie (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding instruction to accommodate plural instruction...
C712S210000, C712S229000
Reexamination Certificate
active
06317822
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to microcontroller architectures, specifically techniques for ensuring compatibility between old and new members of a family of microcontroller architectures.
BACKGROUND OF THE INVENTION
As new microcontroller architectures become feasible due to cost reductions for a variety of reasons and new techniques for improving the performance of microcontrollers become available, it is desirable to provide complete compatibility between old and new members of a family of microcontrollers to protect the investment of customers in program code and expertise with a particular design. These desires result in tradeoffs between optimizing performance of a microcontroller with a new architecture while maintaining complete backwards compatibility. The present invention has particular application to an existing microcontroller sold under the product name MCS-51 by Intel Corporation and a new microcontroller known as MCS-251, also available from Intel Corporation. The major differences between the architectures of the two microcontrollers are as follows:
1. Extended code and data spaces: The MCS-51 has 256 bytes of internal data, 64K of external data, and 64K of program memory. The MCS-251 in comparison has 16M, extendible to 4G, of single address space.
2. Unified address space: Single address space in the MCS-251 makes CPU and compiler implementations easier. In the MCS-51, program memory, data memory and internal registers each lie in a separate address space.
3. Extended stack: MCS-251 provides 64K of stack space (Extendible to 4G) compared to 256 bytes on the MCS-51.
4. Extended bit addressability: In the MCS-251, the special function registers (SFRs) and directly addressable RAM are bit addressable.
5. Extended register file: MCS-251 architecture has 24 more bytes of registers than the MCS-51 architecture.
6. Instruction set: The MCS-251 architecture provides an instruction set which is a superset of the MCS-51 instruction set.
7. Availability of extended address space: The MCS-251 architecture makes the MCS-251 extended address spaces accessible to the MCS-51 instruction set. This allows existing users to utilize their investments in MCS-51 software tools to tap the benefits of the MCS-251 architecture.
In the following description, the techniques of the present invention are described with reference to the MCS-51 and the MCS-251 architectures. However, the references to these two architectures are for convenience in describing the invention with respect to real world examples. Persons skilled in the art will recognize that the invention has application to other architectures as well.
SUMMARY OF THE INVENTION
The present invention is directed to address space, code and instruction encoding extensions to a microcontroller architecture which provide backward compatibility with an existing microcontroller while allowing significant performance enhancements as a result to the new architecture. The extensions are based on the following architectural tradeoffs:
Address Space Extension
The MCS-51 architecture has 256 bytes of internal data, 64K of external data, and 64K of program memory. The MCS251 in comparison has 16M (extendible to 4G) of single address space.
The internal data memory of the MCS-51 architecture is mapped at address 0 of the MCS-251 architecture. This removes the architectural restriction on internal RAM size. It further allows a stack larger than 256 bytes without losing MCS-51 code compatibility. The stack rolls out from internal memory to external memory thus making an external stack available to existing MCS-51 programs.
The external data memory is mapped at 64K on the MCS-51 architecture. This allows instructions which move data to/from a register or accumulator from/to external memory to map to external memory (as long as there is no internal memory at 64K) without restricting the size of the internal RAM.
Program memory is mapped to FF0000. This allows the external bus, which is used for data transfer operations, to be extended beyond a 16-bit address while keeping compatibility with the MCS-51 port reset value of FF.
{overscore (PSEN)} (program store enable) or read strobe for external fetches and {overscore (RD)} (read) are the code and data strobes respectively for the MCS-51 architecture. The MCS-251 architecture unifies the code and data space by making {overscore (PSEN)} and {overscore (RD)} both address mapped code/data read strobes. This makes {overscore (PSEN)}/{overscore (RD)} partitioning transparent to the software tools which do not see separate code and data spaces, but a single address space.
The MCS-51 registers R
0
-R
7
(in four banks or 32 bytes total) have been extended to a 64 byte register file. The MCS-51 address and data registers have been mapped to this register file. This ensures compatibility while allowing the MCS-251 instructions to be used to manipulate MCS-51 registers. The data pointer (DPTR) and stack pointer (SP) are extended in the MCS-251 architecture. This allows MCS-51 users to address the MCS-251 address space, and allows them to use a larger stack.
The MCS-51 special function registers (SFRs) are carried over to the MCS-251 architecture without changing the addresses. The extended stack pointer and the data pointer have been mapped to the SFR space to allow using MCS-51 instructions to address beyond the MCS-51 address space.
Extensions to Provide MCS-51 Code Compatibility
All MCS-51 instructions retain their functionality on MCS-251. Any code relative addressing reference the current 64K page where instructions are under execution.
There are two interrupt transfers available on the MCS-251 architecture. One is fully compatible with the MCS-51 architecture. It pushes two bytes of the program counter (PC) on the stack before jumping to the interrupt vector. The instruction return from interrupt (RETI) pops two bytes of PC. This mode allows existing code which uses the instructions return from subroutine (RET) and return from interrupt (RETI) interchangeably to work. The limitation is that the code size is restricted to 64K.
The preferred mode pushes a new program status word (PSW
1
) of the MCS-251 and all 3 bytes of the PC. The RETI instruction pops the pushed bytes. Pushing the PSW
1
ensures that interrupt service routines written for the MCS-51 can be used with new code for the MCS-251 which relies on the Z and N flags of the PSW to be unchanged. The last two bytes pushed are in the same order in the MCS-251 architecture as they are on the MCS-51 architecture. This ensures that any code that alters the return address will work.
MCS 251 Instruction Encoding
The MCS-51 architecture provides one unused opcode which does not leave much room for an architectural extension to provide additional instructions. However, changing the instruction set compromises the compatibility. Therefore, to address this issue, the MCS-251 architecture provides two modes of operation: namely binary and source modes. The entire instruction set is available in both modes, but the encoding is different. The encoding is arranged to simplify decoding. The two modes have different applications.
a) Binary Mode
In the binary mode, all 111 of the MCS-51 instructions (49 of which are single byte, 45 of which are two bytes and 17 of which are three bytes) keep their encoding. The additional MCS-251 instructions have an A5H prefix, A5H being the single unused MCS-51 opcode. This mode allows any new code to be linked to existing binaries to run without changing. Any non MCS-51 instruction however has a 1 byte size penalty and a 1 state execution time penalty. This mode is suitable for users with large existing code who do not mind the penalty for a small percentage of their code.
b) Source Mode
In the MCS-51 architecture, 32 of the 111 instructions, referred to as register instructions, using Rn (register n) or @Ri (indirect RAM address based on the address contained in register i where i is 0 or 1) in the address field, occupy 160 opcodes. In source mode, these instructions have the A5 prefix, thereby freeing
Blakely , Sokoloff, Taylor & Zafman LLP
Chan Eddie
Intel Corporation
Patel Gautam R.
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