Semiconductor device and method for manufacturing the same

Details Semiconductor device and method for manufacturing the same Semiconductor device and method for manufacturing the same

1999-10-29

2001-12-04

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S755000, C257S757000, C257S758000, C438S622000, C438S630000, C438S637000, C438S647000, C438S655000, C438S656000, C438S657000

Reexamination Certificate

active

06326691

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device with wiring which has contacts of low resistance.
2. Description of the Related Art
FIGS. 1-3
are cross sectional views, illustrating a method for manufacturing a first conventional semiconductor device, i.e. a DRAM (Dynamic Random Access Read Write Memory). First, an element-separating oxide film
2
is formed on a P-type silicon substrate
1
, thereby separating the surface thereof into a memory cell region
1
a
and a peripheral circuit region
1
b.
Then, a gate insulating film
3
is formed on the P-type silicon substrate
1
. Gate electrodes
4
each of which is incorporated in a transistor
6
for data transmission are provided on the gate insulating film
3
in the memory cell region
1
a.
A gate electrode for a driving transistor (not shown) is formed on the gate insulating film
3
in the peripheral circuit region
1
b.
Subsequently, ions of an impurity are injected into the P-type silicon substrate
1
, using as masks the gate electrodes of the transistors
6
for data transmission and the gate electrode of the driving transistor. As a result, diffusion layers
15
and
5
for forming the source and drain regions of the driving transistor and the data-transmitting transistors
6
are formed in the P-type silicon substrate
1
. In other words, the data-transmitting transistors
6
each consisting of the gate insulting film
3
, the gate electrode
4
and the diffusion layer
5
serving as the source/drain region are formed in the memory cell region
1
a.
The driving transistor is formed in the peripheral circuit region
1
b.
The memory cell region has a capacity for data accumulation. These transistors
6
and the data accumulation capacity form one memory cell.
Thereafter, an insulating film
7
is formed on the side surfaces and the upper surfaces of the gate electrodes
4
. An interlayer insulating film
8
is formed on the insulating film
7
, the P-type silicon substrate
1
, and the element-separating oxide film
2
. Then, a first contact hole
8
a
for a bit line is formed in the interlayer insulating film
8
such that the hole
8
a
is aligned with the gate electrodes
4
, by the use of FOBIC (Fully overlapping Bitline Contact) described in 1987 Symposium on VLSI Technology, Digest of Technical Papers, p. 93. Subsequently, a second contact hole
8
b
is formed in the interlayer insulating film
8
in the peripheral circuit region
1
b.
As is shown in
FIG. 2
, a polysilicon film
9
having a thickness of about 1000 Å is deposited on the interlayer insulating film
8
and on the inner surfaces of the first and second contact holes
8
a
and
8
b
by means of the CVD (Chemical vapor Deposition). Thereafter, about 5×10
15
cm
−2
of ions of an N-type impurity
10
such as phosphorus or arsenic are injected into the P-type silicon substrate
1
, using the interlayer insulating film
8
as a mask. As a result, N-type diffusion layers
11
and
12
of high density are formed in the surface portions of the substrate
1
which are located under the first and second holes
8
a
and
8
b.
Thereafter, as is shown in
FIG. 3
, a WSi
2
film
13
having a thickness of about 2000 Å is deposited on the polysilicon film
9
by sputtering. Then, the WSi
2
film
13
and the polysilicon film
9
are patterned by the lithography and the RIE (Reactive Ion Etching), thereby forming a bit line
14
as a polycide wire which has a laminated structure of the WSi
2
film
13
and the polysilicon film
9
. The WSi
2
film
13
is annealed at a relatively high temperature, e.g. 800-950° C., so as to activate the diffusion layer and stabilize the film
13
.
Since in the above-described first conventional semiconductor device, the P-type silicon substrate
1
and the polysilicon film
9
contact each other in the first and second contact holes
8
a
and
8
b,
the contact resistance in each of the holes cannot be reduced, although the rate of PN-junction failure can be reduced. As regards the contact resistance of the bit line contact in the memory cell region
1
a,
it suffices if the contact resistance is lower than the channel resistance of the data-transmitting transistor
6
. This means that the contact resistance of the bit line is not necessarily set to a very low value, and may be set, for example, to about 1 k&OHgr;. On the other hand, the contact resistance in the second contact hole
8
b
in the peripheral circuit region
1
b
must be set to a low value with respect to the channel resistance of the driving transistor, i.e., to a value of as low as several tens &OHgr;. The above-described manufacturing method cannot satisfy the requirement that the contact resistance in the peripheral circuit region
1
b
be kept to a very low value, as the degree of integration increases.
FIGS. 4 and 5
are cross sectional views, illustrating a method for manufacturing a second conventional semiconductor device. In these figures, elements similar to those employed in the first conventional semiconductor device are denoted by corresponding reference numerals, and an explanation will be given of only different elements.
As is shown in
FIG. 4
, a laminated film
21
consisting of a TiN upper layer and a Ti lower layer is formed, by sputtering, on the interlayer insulating film
8
and on the inner surface of each of the first and second contact holes
8
a
and
8
b.
Then, the resultant structure is annealed at a relatively low temperature, for example, of about 600° C., thereby forming a TiSi
2
film on the bottom of each of the first and second contact holes
8
a
and
8
b.
Thereafter, as is shown in
FIG. 5
, a metal film
22
of W or the like is deposited on the laminated film
21
by the CVD. Subsequently, the metal film
22
and the laminated film
21
are patterned by the lithography and the RIE, thereby forming in the memory cell region
1
a
a bit line
23
consisting of the laminated film
21
and the metal film
22
.
As described above, in the above-described second conventional semiconductor device, the P-type silicon substrate
1
contacts the Ti lower layer of the laminated film
21
in each of the first and second contact holes
8
a
and
8
b.
Therefore, the contact resistance is made low in the contact holes
8
a
and
8
b,
but the rate of pn-junction failure is high since a silicide is formed as a result of reaction of Ti and Si in the contact portion of the P-type silicon substrate
1
and the Ti layer. In other words, silicon contained in the N-type diffusion layers
11
and
12
becomes a silicide as a result of reaction of Ti and Si in the contact portion, so that pn-junction failure is liable to occur in the N-type diffusion layers
11
and
12
.
Forming deep N-type diffusion layers
11
and
12
is considered to prevent the failure. However, although deep diffusion layers can prevent the failure, they reduce the withstand voltage between adjacent elements. This is because the distance between the adjacent elements is shorten as their size is reduced. Therefore, the diffusion layers
11
and
12
cannot actually be made deep, and accordingly the pn-junction failure cannot be prevented.
The occurrence of the pn-junction failure is especially disadvantage to the bit line contacts in the memory cell region
1
a,
since the number of the bit line contacts in the memory cell region
1
a
is much larger than that of the contacts in the peripheral circuit region
1
b.
Specifically, where the number of the contacts in the peripheral circuit region
1
b
is several tens thousands, the number of the bit line contacts in the memory cell region
1
a
is several millions. Thus, the method for manufacturing the second conventional semiconductor device cannot satisfy the requirement that the rate of pn-junction failure in the memory cell region
1
a
be kept low.
FIG. 6
is a cross sectional view, showing a CMOS DRAM as a third conventional semiconductor device. In

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