Fir filter based upon squaring

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

Reexamination Certificate

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Details

C708S319000

Reexamination Certificate

active

06330579

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to digital filtering of electronic signals, and more particularly to an improved finite impulse response (FIR) filter based upon squaring that uses the filter itself to determine a constant equal to the sum of the squares of the filter coefficients.
U.S. Pat. No. 5,561,616, issued to the present inventor on Oct. 1, 1996 entitled “FIR Filter Based Upon Squaring”, illustrates a FIR filter based on squaring that reduces the complexity of the filter as opposed to standard FIR filter convolutions. At the output of the FIR filter is a subtracting circuit which has as one of the inputs a constant equal to the sum of the squares of the filter coefficients. The sum of the squares of the coefficients is indicated as being determined in a non-real-time manner with minimal hardware, by pre-calculation, or externally as an entry with each new set of coefficients as they are loaded.
Also once the set of coefficients is loaded into the filter, when the filter is coupled to a processor bus where multiple devices may access the filter, it is sometimes desirable to be able to determine what the coefficients of the filter are. A shadow set of values may be kept in a central processing unit (CPU) coupled to the bus from which the FIR filter was loaded, but this does not allow testing of the FIR filter by reading back the filter coefficients that were written. Or the coefficient inputs of the filter itself may be tied into a separate filter bus for reading back the filter coefficients, but this adds to the complexity of the FIR filter.
What is desired is an improved FIR filter based on squaring where the modification provides a way to easily determine the sum of the squares of the coefficients, while being accessible to external devices on a processor bus.
BRIEF SUMMARY OF THE INVENTION
Accordingly the present invention provides an improved FIR filter based on squaring that has the capability of computing the sum of the squares of the filter coefficients for use by the filter as well as providing the ability for an external device coupled to the bus to determine the coefficients currently loaded into the FIR filter. The input signal is forced to zero for T samples, where T is the number of accumulator stages, or taps, of the filter. At the end of T zero samples the output is latched to store the constant for use in the final subtraction stage of the filter. The filter may also be used as a co-processor by providing a FIFO interface with a CPU bus. The CPU, when it initiates the co-processor mode, disables the external input signal and itself clocks and loads data values into the FIFO. When the FIFO has data, then it is read out into the input of the filter as a data sample and a local filter clock is generated. The output of the filter is returned to the CPU via the bus. To determine what the loaded filter coefficients are, the data loaded into the FIFO by the external device is an impulse signal represented by T−1 zero samples both before and after an impulse sample. The outputs from the filter then represent each of the filter coefficients.


REFERENCES:
patent: 5500811 (1996-03-01), Corry
patent: 5561616 (1996-10-01), Slavin

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