Analog to digital converter using remainder feedback loop

Details Analog to digital converter using remainder feedback loop Analog to digital converter using remainder feedback loop

2000-12-21

2001-12-25

Wamsley, Patrick (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S172000

Reexamination Certificate

active

06333709

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a CMOS logic circuit, an AD converter and DA converter using capacitive coupling, and to an innovative circuit that can reduce the number of circuit elements required for logic circuits, AD converters and DA converters, which together with a photoelectric conversion device, such as an image sensor, are integrated in a single LSI.
2. Related Arts
For the fundamental structure of a CMOS logic circuit, comparatively many CMOS transistor elements are employed, as, for example, is described in “Base of MOS Integrated Circuit” (Kindai Kagakusha, May 30, 1992). AD converters are described, for example, in “Transistor Techniques Special, No. 16” (CQ Publication, Feb. 1, 1991, Second Edition). A flash AD converter that can obtain output at the same time as input being applied is better as an AD converter integrated with a photoelectric conversion device, such as an image sensor. However, the flash AD converter requires many comparators, and accordingly, the volume of the circuit is increased. For example, 2
n
−1 comparators are required to constitute an n-bit AD converter.
An image sensor has been studied wherein a signal processing function is provided on the chip by forming a CMOS circuit on the same substrate and whereby digital output is enabled. Such an image sensor is described, for example, in “Proceedings of SPIE Vol. 2745 Infrared Readout Electronics III” pp. 90-127, Apr. 9, 1996.
As is described above, however, the current CMOS logic circuit has many elements, and the AD converter which converts an analog signal detected by a sensor into a digital signal also has many elements. If a digital circuit employing these circuits is formed on the same substrate as is a photosensor, a fill-factor, which is a ratio of the sensor area to the area of the entire chip, is extremely small. This is described, for example, in ISSCC 1994 Digest Of Technical Papers, pp. 230.
SUMMARY OF THE INVENTION
It is, therefore, one object of the present invention to provide a CMOS logic circuit that has a very small number of elements.
It is another object of the present invention to provide a CMOS AD converter that does not require many comparators and for which only a few elements are employed.
It is an additional object of the present invention to provide a flash CMOS AD converter for which only a few elements are employed.
It is a further object of the present invention to provide a time sharing CMOS AD converter for which only a few elements are employed.
It is still another object of the present invention to provide a CMOS DA converter for which only a few elements are employed.
It is a still further object of the present invention to provide an image sensor, on which is mounted a digital circuit with a few devices, that can increase its fill-factor.
To achieve the above objects, according to the present invention, a logic circuit comprises:
a plurality of input terminals, to which binary input is provided;
a plurality of input capacitors having first electrode respectively connected to one of the plurality of input terminals and second electrode connected in common, said input capacitors having almost the same capacitance; and
an inverter circuit, for receiving a voltage from the second electrodes and having a threshold value so that the inverter circuit is inverted when a voltage corresponding to logic 1 is applied to a predetermined number of input terminals of the plurality of input terminals.
Since a capacitive coupling circuit is employed in which a plurality of input capacitors are coupled in common and input signals are supplied to each input capacitors, when a voltage corresponding to logic 1 is applied to a predetermined number of input capacitors, a potential exceeding a threshold value of an inverter can be generated at the coupling terminal. When, for example, the threshold value is set to half of the power voltage, the logic circuit serves as a majority circuit.
In addition, when a fixed potential is applied to some input terminals connected to the input capacitors, a NAND circuit and an AND circuit, and a NOR circuit and an OR circuit can be obtained.
Further, developing the logic circuit, a logic circuit, such as a flip-flop circuit or a full adder, can be constituted by a small number of transistors.
As another feature of the present invention, by using a capacitive coupling circuit an analog/digital converter can be constructed for which only an extremely small number of transistors are employed. An example thereof is an analog/digital converter having an input terminal, for which analog input is provided and N (N is a plural value) bits output terminals, for which binary output is provided, comprises:
N unit circuits arranged in parallel, each including
an input capacitor having a first electrode connected to the input terminal,
a first inverter connected to a second electrode of the input capacitor, and
a second inverter connected to the first inverter,
wherein outputs of the second inverters of the unit circuits are respectively provided for the output terminals,
inverted outputs of the outputs for the unit circuits are fed back via feedback capacitors to inputs of the first inverters of the unit circuits respectively corresponding to lower bit, and
a capacitance of the feedback capacitor, which corresponds to the inverted output of the M-th (M is an integer) unit circuit from the most significant bit, is ½
M
of a capacitance of the input capacitor of the unit circuit that is fed back.
When inverted signals for upper bit digital outputs are transmitted via feedback capacitors to the input of the lower bit inverters, lower bit comparison potentials can be generated by the capacitive coupling circuits. The above A/D converter can be constituted by an innovative CMOS circuit having an extremely small number of transistors.


REFERENCES:
patent: 3260863 (1966-07-01), Burns et al.
patent: 5027116 (1991-06-01), Armstrong et al.
patent: 5258657 (1993-11-01), Shibata et al.
patent: 5274377 (1993-12-01), Matsuura et al.
patent: 5402128 (1995-03-01), Kusumoto et al.
patent: 5444411 (1995-08-01), Yang et al.
patent: 5594372 (1997-01-01), Shibata et al.
patent: 5644253 (1997-07-01), Takatsu
patent: 5812079 (1998-09-01), Ito et al.
patent: 5818380 (1998-10-01), Ito et al.
patent: 5982315 (1999-11-01), Bazarjani et al.
patent: 6043675 (2000-03-01), Miyamoto
patent: 6107950 (2000-08-01), Fisher et al.

Affiliated with

Also associated with

Rating

Analog to digital converter using remainder feedback loop does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Analog to digital converter using remainder feedback loop, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Analog to digital converter using remainder feedback loop will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2600512