Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
1999-04-16
2001-10-02
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S456000, C438S422000
Reexamination Certificate
active
06297072
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related to a microstructure product and a method of fabricating of a microstructure having an internal and preferably sealed cavity.
The present invention is also related to specific applications of this method of fabricating of a microstructure.
BACKGROUND
Microstructures having an internal cavity can be formed by making an assembly of two chips or two wafers or a chip-on-wafer with a spacer in-between. Such structures should have hermetically sealed cavities filled with a controlled ambient (gas composition and/or pressure).
These structures can be used for many different applications such as microaccelerometers, microgyroscopes, microtubes, vibration microsensors, micromirrors, micromechanical resonators or “resonant strain gauges”, micromechanical filters, microswitches and microrelays.
Traditionally, for these applications, the ambient of the cavity is defined during the assembly of the several components by anodic, fusion or eutectic wafer bonding, wafer bonding using low temperature glasses or polymers as the brazing material and reactive sealing techniques.
A common drawback of these techniques is that they are rather limited in applicability, since device separation is difficult (the device has been made on one of the two wafers). It is also difficult to create electrical contacts. The drawbacks of three of the most common techniques are discussed herebelow.
The technique of diffusion bonding of a Si cap wafer on the device wafer requires flat Si surfaces and a high temperature process.
Wafer bonding techniques such as anodic bonding and silicon fusion bonding require a very clean environment, i.e., low particle contamination. There are applications that are not compatible with these boundary conditions of temperature and flatness. Furthermore, the technique of anodic bounding also requires flat surfaces and needs the application of a high voltage in order to achieve the bonding.
Finally, the technique of gluing does not provide a real hermetic bond.
U.S. Pat. No. 5,296,408 describes a fabrication method of making a microstructure having a vacuum sealed cavity therein, including the process steps of forming an aluminum filled cavity in a body of silicon material and heating the structure such that the aluminum is absorbed into the silicon material leaving a vacuum in the cavity. In one embodiment, a cavity is etched into a silicon wafer and filled with aluminum. A silicon dioxide layer is formed over the aluminum filled cavity and the structure is heated to produce the vacuum cavity.
The document “Fluxless flip-chip technology” by Patrice Caillat and Gérard Nicolas of LETI, published at the First International Flip-Chip Symposium, San Jose, Calif., February 1994 describes a flip-chip assembly of two chips with a solder sealing ring defining a cavity during the assembly itself. The assembly and the subsequent sealing are normally done in air or under an N
2
purge. Similar conditions may exists for the other wafer bonding techniques as mentioned hereabove (except for the technique of reactive sealing).
Advantages of the Present Invention
The present invention is directed to a microstructure product and a method of fabricating a microstructure having an internal cavity. Preferably, the covity is sealed with a controlled ambient allowing a free choice of the sealing gas composition and the sealing pressure or vacuum.
The method preferably does not require special equipment to perform the fabrication of such microstructures in a vacuum or controlled inert gas ambient.
The method is suited for micro-electromechanical systems (MEMS) packaging wherein all the process steps are compatible with packaging equipment.
SUMMARY OF THE PRESENT INVENTION
The present invention is related to a method of fabricating a microstructure having an inside cavity, comprising:
making a first layer or a first stack of layers in a substantially closed geometric configuration on a first substrate;
creating an indent on the first layer or on the top layer of said first stack of layers;
making a second layer or a second stack of layers substantially with said substantially closed geometric configuration on a second substrate;
aligning and bonding said first substrate to said second substrate such that a microstructure having an inside cavity is formed according to said closed geometry configuration.
The indent preferably is formed with a groove made in one of the a layers such that when the two substrates are secured together, a connection, preferably a contacting channel, between the inside cavity of a microstructure and the outside ambient is created.
Such an indent can be made using a variety of different techniques including lithographic and/or chemical techniques or mechanical techniques removing a part of the first layer using a tool such as a shearing tool or cutting tool by applying a force using an indent tool on the first layer or by other steps.
As used herein, the term “making a layer on a substrate” means any type of method of providing a layer as the substrate including depositing or growing a layer on the substrate.
After the two substrates are secured together the indent is closed by reflowing the first layer at a reflow temperature. The reflow temperature is preferably at a temperature at which said first layer, or at least the top layer of the first stack of layers, is fusible but not the substrate and/or the other materials thereon. The reflow temperature can be lower than the melting temperature of the first layer or of one of the layers (the top layer) of the first stack of layers, the temperature being just high enough to achieve the closing of the indent and/or the corresponding fusion of the two substrates. The reflow temperature can also be equal to or above said melting temperature. Thus the reflow temperature is the temperature at which the first layer or the top layer of the first stack of layers has sufficient plasticivity to reflow for closing the indent and achieving at the same time the fusion of the two substrates.
The inside cavity can contain any kind of device with a predetermined vacuum or inert gas (N
2
, He, Ar, Xe, . . . ) atmosphere or any other kind of gaseous atmosphere.
One of the embodiments of the present invention makes use of a solder sealing ring that can be combined with standard solder bumps for electrical contact.
Advantages of the technique of the present invention include flexible packaging of devices. A good electrical contact between device and package is also made possible, the second or the first substrate can be a more complex device by itself, a hermetic cavity sealing can be achieved and the technique can be executed to a large extent at wafer-level.
It is a further advantage of bonding techniques based on a solder bond, that are less susceptible to particles. Furthermore, flip-chip solder bonds also have the interesting property of self-alignment (within certain limits) and display a good control, predictability and reproducibility of the solder height and thus the cavity height. Furthermore, a solder bond leads to a metallic seal, which is known to provide the best hermeticity possible. Also, the metallic seal can be used as an electrical feedthrough from one chip (e.g. the bottom chip) to the other (e.g. the top chip of the stack).
Further characteristics or advantages will be found in the following description of several preferred embodiments of the present invention.
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Beyne Eric
Tilmans Hendrikus A. C.
Van de Peer Myriam
Everhart Caridad
Interuniversitair Micro-Elktronica Centrum (IMEC VZW)
Knobbe Martens Olson & Bear LLP
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