Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
1999-09-29
2001-12-04
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C323S315000
Reexamination Certificate
active
06326836
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a bias generating apparatus, and particularly to current mirroring, and more particularly to current mirroring not having a common reference node.
BACKGROUND OF THE INVENTION
In the current mirror shown in
FIG. 1
100
transistor Q
1
103
accepts input current Iin and is connected to transistor Q
2
105
whereby the transistor output current Iout is related in magnitude and direction to Iin by the transconductance of the transistors. This is due to the common voltage from base to emitter (VBE) of the transistors Q
1
and Q
2
as connected. When used with transistors, and especially in a circuit using bipolar transistors, the relationship between the input current to Q
1
103
and output current received by Q
2
105
may be precisely controlled.
In the prior art, both transistors in a current mirror as shown in
FIG. 2
have a common emitter connection referred to as the reference node, which in the case of bipolar transistors is commonly the emitter nodes or through resistors in the emitter nodes of the transistors. The VBE of the input transistor with respect to the reference node controls the VBE of the output transistor with respect to the reference node.
It is often desirable that the reference node of the output transistor be connected to some other point than the reference node of the input transistor. This can be a requirement, for example, for an operational amplifier, where mirroring is used extensively, but the output may be referenced to a different voltage than the input reference; that is, there is some degree of isolation between input and output.
In an embodiment of the prior art shown in
FIG. 2
200
, transistor
203
, an NPN bipolar transistor in this embodiment, accepts an input current Iin and sets a VBE reference for transistor
207
. Optional transistor
205
prevents excessive loading of the base connections of
205
and
207
, but is often not included. The output from transistor
207
is received by transistors
209
and
211
, wherein transistor
211
is optional, as discussed before. In like manner, transistor
213
provides an output current to transistors
215
and
217
, and the final output current lout is supplied by transistor
219
. Note that transistors
209
,
211
, and
213
are PNP transistors, since alternating transistor polarity types between stages, where transistors
203
,
205
, transistors
207
,
209
,
211
, and
213
, and transistors
215
,
217
, and
219
are all considered stages, simplifies interstage connections. The addition of the stages needed to avoid a common reference creates a problem in transistor matching, since errors in matching may occur in any stage, and are multiplied by subsequent stages. This can be a problem with respect to emitters, especially with respect to the emitters of PNP current mirrors such as transistors
209
and
213
in the current mirror composed of transistors
209
,
211
and
213
. PNP emitters generally both have a higher impedance and have more impedance across a contact, for example, from a PNP emitter to a connection such as a wire. It is very important where designing for matched impedance is a problem, that differences in emitter impedance, and especially resistance, be minimized.
What is needed is a bias circuit for precise control of the DC current with different reference nodes which is tolerant of emitter impedance effects in the current mirrors, and more particularly to allow an unbalanced impedance in the emitter circuit of the output transistor.
SUMMARY OF THE INVENTION
In a multistage bias current generating circuit having an output and an input referenced to different voltages, the output is referenced only by a control current, and does not depend on transconductance. In this way, an impedance in the reference path of the output does not unbalance the relationship between input and output. Additionally, the current though intermediate stages is reduced to reduce the effects of parasitic impedances. Reducing the current also reduces parasitic effects due to unwanted impedances in the contacts and material, since these effects are essentially current times impedance. The reduced current is then increased back by substantially the same amount as the reduction to provide an output current with a desired relationship with the input. Either an input current or an input voltage will be provided to the circuit.
Other objects, features and advantages of the present invention will become apparent from the following detailed description when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 4507573 (1985-03-01), Nagano
patent: 4857864 (1989-08-01), Tanaka et al.
patent: 5675243 (1997-10-01), Kamata
patent: 5808508 (1998-09-01), Castellucci et al.
patent: 5825236 (1998-10-01), Seevinck et al.
patent: 5942888 (1999-08-01), Tan
patent: 5982227 (1999-11-01), Kim et al.
patent: 6087819 (2000-07-01), Kuroda
Agilent Technologie,s Inc.
Cunningham Terry D.
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