Sharing signal lines in a memory device

Details Sharing signal lines in a memory device Sharing signal lines in a memory device

1999-08-30

2001-02-20

Fears, Terrell W. (Department: 2824)

Static information storage and retrieval

Addressing

C365S230030

Reexamination Certificate

active

06191995

ABSTRACT:

BACKGROUND
The invention relates to sharing signal lines in a memory device.
Memory devices are commonly used as storage units in many types of electronic systems, such as computer systems, consumer electronic devices, game systems, communications systems and devices, and other systems. Various types of memory devices exist, including dynamic random access memories (DRAMs), synchronous DRAMs (SDRAMs), Rambus DRAMs (RDRAMs), static RAMs (SRAMs), double data rate DRAMs (DDR DRAMs), and so forth.
A significant factor in the cost of a memory device is its overall die size. Memory dies are fabricated on a wafer. The number of dies that can be fit onto a wafer depends on the die size. A smaller die size generally allows more dies to be placed on a wafer, which generally increases yield of the manufactured memory dies. Yield refers to the percentage of good dies (i.e., those that are functional and that satisfy certain timing and voltage specifications) out of the total number of dies manufactured. The good dies are cut from the wafer and packaged to form integrated circuit (IC) devices.
Reduced die sizes may also have other advantages. For example, it is desirable to reduce the footprint of integrated circuit (IC) devices on a circuit board, such as the motherboard of a computer system, to allow greater density of IC devices on the circuit board. One way to reduce such IC device footprints is to reduce the package size, which may be made possible by reducing die sizes.
A memory device such as a DRAM, SDRAM, RDRAM, SRAM, DDR DRAM, and the like, generally includes a memory core and peripheral circuitry associated with the memory core. The memory core includes the memory cells, sense amplifiers coupled to the memory cells, row decoders that drive row lines (such as word lines) to activate a row of cells, and other components. The peripheral circuitry generally includes address decode logic, data input and output buffers, multiplexing logic, clock generators, data latches and other logic and circuitry. Because of the number of bits that are stored in memory devices, the memory core typically makes up a large part of the size of a memory device. Select signals (such as address select signals) from the peripheral circuitry are routed into the memory core on signal lines to control access of memory cells in the memory core. Depending on the architecture of the memory device, many of the control signal lines may be repeated several times throughout the memory core. As a result, the space needed for routing such signal lines may take up a substantial part of the size of a memory die. A need thus exists for methods and circuitry that provide for more efficient usage of memory die space by decreasing the number of signal lines.
SUMMARY
In general, according to one embodiment, a memory device includes a plurality of memory cells. First control circuits drive control lines to a first set of memory cells, and second control circuits drive control lines to a second set of memory cells. Shared select lines that are coupled to both the first and second control circuits alternately carry signals associated with the first and second control circuits.
Other features and embodiments will become apparent from the following description and from the claims.


REFERENCES:
patent: 4202044 (1980-05-01), Beilstein
patent: 5493536 (1996-02-01), Aokl
Micron Technology, Inc.,Direct Rambus™Dram, Rev. Feb. 1999, pp. 1-3 (Feb. 1999).
Rambus, Inc.,Rambus® Technology Overview, pp. i-10 (Feb. 12, 1999).
Rambus Inc.,Document DL0059, Version 1.0, Direct RDRAM Preliminary Information, pp. 1-42, dated at least as early as Jul. 6, 1999.

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