Semiconductor storage device

Details Semiconductor storage device Semiconductor storage device

2000-06-22

2001-12-25

Elms, Richard (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S104000, C365S051000

Reexamination Certificate

active

06333867

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor storage device such as mask ROM (mask read only memory) and so forth with more high integration and high speed operation. More to particularly, this invention relates to a semiconductor storage device for the sake of the mask ROM in which a plurality of memory cell transistor (Tr) are connected with every one bit contact due to the fact that it causes main/sub bit line constitution and virtual GND system to be adopted in order to realize large capacity mask ROM with high integration and high speed access.
DESCRIPTION OF THE PRIOR ART
Formerly, the semiconductor storage device is applied to various kinds of the fields as, for instance, a mask ROM (mask read only memory). Storage capacity of the mask ROM increases year after year. At present time, the mask ROM of 256 Mbit is generally produced in large quantities.
A unit cell size in the word direction of the NOR type memory cell is determined according to wiring pitch of sub bit-lines and layout pitch of primary bit-lines. These specifications mainly proceed out of process technology such as lithography, etching, and so forth, thus it is difficult to reduce in the circuit. On the other hand, about a unit cell size in the bit-line direction is determined according to following respective items (A), (B), and (C).
(A): wiring pitch of word selection line
(B): stage number of the memory cell connected in every one bit contact
(C): number of selection line with the exception of word selection line
With respect to item (A), it is determined due to etching precision of poly crystal Si constituting the word selection line, therefore it is caused by process. However, with respect to item (B), it is caused by resistance value within current route of ‘the primary bit-line’ to ‘the sub bit-line’ to ‘the memory cell’ to ‘the sub bit-line’ to ‘the bank selection transistor’ to ‘the virtual GND line’ from the sense amplifier on the occasion of cell selection. Further, with respect to item (C), it is caused by number of the bank selection line in every bit contact. For that reason, it is capable of realizing reduction due to the fact that it causes constitution of memory cell array including the bank selection line and or the bank selection transistor.
With respect to the item (C) described above,
FIG. 1
shows the conventional example 1, and
FIG. 2
shows the conventional example 2 (
FIGS. 1
, and
2
show only diffusion layer, and bank selection transistors). Concerning the present conventional example 1, the Japanese Patent Application Laid-Open No. HEI 3-142877 discloses the memory cell capable of selecting bank row according to four selection signal lines in every one bit contact. In this case, the diffusion layer to which the sense amplifier charges is one side of selection side within above and below memory cell array of the digit contact. Further,
FIGS. 3
, and
4
are views for explaining capacitance of diffusion layer of the conventional example 1 and the conventional example 2.
FIGS. 1
, and
3
show a flat type cell of the mask ROM of the conventional example 1. The flat type cell of the mask ROM is the conventional constitution example in which it causes part should be charged to be reduced while regarding characteristic important.
FIGS. 2 and 4
show the conventional example 2, which is a conventional cell constitution while regarding chip size important. The content of these conventional examples is described in detail while comparing with the embodiment of the present invention.
Further, as the conventional example 3 whose technical field is similar to the present invention, the Japanese Patent Application Laid-Open No. HEI 4-305973 discloses “Semiconductor Storage Device”. The conventional example 3 implements selection of memory transistor group of reading target according to the fact that one of two source lines is set to earth level, the other is set to floating state. For that reason, it is capable of reducing the bit-lines to be formed to the memory transistor group, thus improving degree of integration.
However, improvement of integration collides with acquisition of stabilized good characteristic. Consequently, there is the problem that high integration namely, reduction of area in every unit bit is required, while possessing stabilized good characteristic in future mask ROM.
This is considered while employing the conventional example 1, the conventional example 2, and the conventional example 3 which have different characteristic described above. The chip size is not intended to be enlarged as the conventional example 1. The conventional examples 2, and 3 have defect in characteristic. There occurs problem that it causes chip size to be reduced while suppressing deterioration of characteristic.
SUMMARY OF THE INVENTION
In view of the foregoing, it is an object of the present invention, in order to overcome the above-mentioned problem, to provide a semiconductor storage device which is capable of realizing high integration and high speed access.
According to a first aspect of the present invention, in order to achieve the above-described object, there is provided a semiconductor storage device which comprises one contact which is connected to a primary bit-line, five sub bit-lines which are connected to the primary bit-line through four bank selection transistors, one contact which is connected to a virtual GND line, and two sub bit-lines which are connected to the virtual GND line through two bank selection transistors, wherein respective six sub bit-lines are arranged in parallel to signal inputted to six bank selection lines and are arranged in parallel to the primary bit lines, thus selecting memory cell transistor due to combination of level of two virtual grand lines arranged at right and left of the primary bit lines.
According to a second aspect of the present invention, in the first aspect, there is provided a semiconductor storage device, wherein ‘right and left’ of one sub bit-line with contact connected to the primary bit-line as center is segregated into upper part and lower part with respect to the contact connected to the primary bit-line, and ‘right and left’ of one sub bit-line with contact connected to the virtual GND line as center is connected by ‘above and below’ sub bit-line with respect to the contact connected to the virtual GND line.
According to a third aspect of the present invention, in the first or second aspect, there is provided a semiconductor storage device, wherein the virtual GND line is connected to either a pre-charge circuit or GND through a row select transistor controlled by a row selection line and a virtual GND selection transistor controlled by virtual GND selection signal.
According to a fourth aspect of the present invention, there is provided a semiconductor storage device which comprises one contact which is connected to a primary bit-line, two sub bit-lines which are connected to the primary bit-line through two bank selection transistors, one contact which is connected to a virtual GND line, and five sub bitlines which are connected to the virtual GND line through four bank selection transistors, wherein respective six sub bit-lines are arranged in parallel to signal inputted to six bank selection lines and are arranged in parallel to the primary bit lines, thus selecting memory cell transistor due to combination of level of two virtual grand lines arranged at right and left of the primary bit lines.
According to a fifth aspect of the present invention, in the fourth aspect, there is provided a semiconductor storage device, wherein ‘right and left’ of one sub bit-line with contact connected to the primary bit-line as center is connected by ‘above and below’ sub bit-line with respect to the contact connected to the primary bit-line, and ‘right and left’ of one sub bit-line with contact connected to virtual GND line the as center is segregated into upper part and lower part with respect to the contact connected to the virtual GND line.
According to a sixth aspect of the present invention, in t

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