Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2000-12-22
2001-12-11
Kim, Jung Ho (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S513000, C323S315000
Reexamination Certificate
active
06329871
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a reference voltage generation circuit, more particularly, to a reference voltage generation circuit which can be suitably built in an integrated circuit formed by integrating metal insulation semiconductor (MIS) transistors, specifically metal oxide semiconductor (MOS) transistors, such as insulated-gate field-effect transistors.
2. Description of the Related Art
For example, a dynamic random access memory (DRAM) includes a voltage reduction circuit which reduces a reference voltage such as 5 [V] supplied from outside to 3 [V], and uses the reduced voltage as an internal power supply voltage. A reference voltage generation circuit is necessary for forming such a voltage reduction circuit.
Also, a reference voltage generation circuit is necessary when an analog integrated circuit, such as a D/A converter for converting a digital signal to an analog signal, or an A/D converter for converting an analog signal to a digital signal, is constructed.
Generally, it is preferable that a reference voltage is a constant voltage which does not depend on the temperature. In a MOS integrated circuit, however, an operation speed is proportional to a power supply voltage and is inversely proportional to the temperature. Accordingly, it is preferable that a reference voltage has positive temperature characteristics especially when the reference voltage is used in a voltage reduction circuit for generating an internal power supply voltage.
On the other hand, in an integrated circuit, an increase in production processes thereof leads to a resulting increase in cost and thus a reference voltage generation circuit to be built in the integrated circuit must have a formation which does not increase the production processes.
However, a known reference voltage generation circuit needs to be produced using a so-called “triple-well process”, while a typical MOS integrated circuit can be produced using a so-called “twin-well process”. Namely, when such a reference voltage generation circuit is incorporated into a typical MOS integrated circuit, a problem occurs in that the entire production process is increased due to the difference of the number of wells, i.e., the difference of the number of processes, and thus the cost of production is similarly increased.
Also, another reference voltage generation circuit is known in which it is difficult to restrict a consumed current therein to a predetermined amount or less. In this case, it would be possible to reduce the consumed current by setting a resistance value of a circuit element which determines the consumed current, to a greater value.
However, such an approach to reduce the consumed current is not practical since a considerably large area in the MOS integrated circuit is necessary in order to form such a resistance element.
Furthermore, when an external power supply voltage fed to a reference voltage generation circuit fluctuates in level, a problem occurs in that the generated reference voltage extremely becomes unstable depending on the temperature characteristics thereof.
Note, the problems in the prior art will be explained later in detail in contrast with the preferred embodiments of the present invention.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a reference voltage generation circuit which can obtain a stable reference voltage.
Another object of the present invention is to provide a reference voltage generation circuit which can be built in an integrated circuit produced by integrating MIS transistors such as insulated-gate field-effect transistors, without introducing an increase in production processes.
Still another object of the present invention is to provide a reference voltage generation circuit which can reduce a consumed current thereof.
According to a first aspect of the present invention, there is provided a reference voltage generation circuit comprising: load means having one end thereof connected to a higher voltage power supply line; an enhancement type n-channel MIS transistor having a drain thereof connected to the other end of said load means, and a source thereof connected to a lower voltage power supply line; and a source follower circuit using a MIS transistor as a driving element, the source follower circuit having an input end thereof connected to the drain of said n-channel MIS transistor and having an output end thereof connected to a gate of said n-channel MIS transistor; wherein i reference voltage is obtained at the drain of said n-channel MIS transistor.
Also, according to a second aspect of the present invention, there is provided a reference voltage generation circuit comprising: load means having one end thereof connected to a higher voltage power supply line; an enhancement type n-channel MIS transistor having a drain thereof connected to the other end of said load means, and a source thereof connected to a lower voltage power supply line; and a plurality of source follower circuits using MIS transistors as driving elements, respectively, and connected in a cascade connection, an input end of a source follower circuit at the first stage in the cascade connection being connected to the drain of said n-channel MIS. transistor, an output end of a source follower circuit at the final stage in the cascade connection being connected to a gate of said n-channel MIS transistor; wherein a reference voltage is obtained at the drain of said n-channel MIS transistor.
REFERENCES:
patent: 4204133 (1980-05-01), Ahmed
patent: 4409677 (1983-10-01), Takemae et al.
patent: 4490670 (1984-12-01), Wong
patent: 4616172 (1986-10-01), Rahim
patent: 4645998 (1987-02-01), Shinohara et al.
patent: 4868483 (1989-09-01), Tsujimoto
patent: 5218238 (1993-06-01), Nonaka et al.
patent: 5434533 (1995-07-01), Furutani
patent: 5483150 (1996-01-01), Elliot et al.
patent: 5798637 (1998-08-01), Kim et al.
patent: 5818292 (1998-10-01), Slemmer
patent: 5959446 (1999-09-01), Kuckreja
patent: 5982227 (1999-11-01), Kim et al.
patent: 6002276 (1999-12-01), Wu
patent: 6107868 (2000-08-01), Diniz et al.
patent: 43 31 895 (1994-03-01), None
patent: 0 594 162 (1994-04-01), None
P. Horowitz, et al.,The Art of Electronics, p. 228, Figure 6.11, Cambridge University Press, 1980.
Research Disclosure,Variable Response, On Chip, Low Voltage Supply, (Feb. 1990), No. 310.
IBM Technical Disclosure Bulletin, vol. 32, No. 10A, Mar. 1990, pp. 26-28.
Japanese Abstracts, 06-104672(A), Apr. 1994, Takeshi Kajimoto (Mitsubishi Electric Corp.) (corresponding to German document 43 31 895, cited above).
Armstrong Westerman Hattori McLeland & Naughton LLP
Fujitsu Limited
Kim Jung Ho
LandOfFree
Reference voltage generation circuit using source followers does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Reference voltage generation circuit using source followers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reference voltage generation circuit using source followers will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2597542