Coded data generation or conversion – Converter compensation
Reexamination Certificate
2000-08-28
2001-11-27
JeanPierre, Peguy (Department: 2819)
Coded data generation or conversion
Converter compensation
C341S120000
Reexamination Certificate
active
06323792
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the art of analog-to-digital converters (ADCs), and more particularly, to correcting ADC errors.
DESCRIPTION OF THE RELATED ART
Analog-to-digital converters (ADCs) are circuits widely used to interface between the physical world of analog quantities and the computational world of digital processors. Analog quantities such as temperature, pressure, flow rate, and velocity, vary in a continuous manner between extremes. Transducers of measurement and control systems convert such analog quantities to analog electrical signals (e.g., analog voltages or currents). ADCs are used to convert analog electrical signals to discrete digital values. Known types of ADCs include flash, delta-sigma (or sigma-delta), sub-ranging, successive approximation, and integrating.
A typical n-bit ADC receives an analog input quantity (e.g., an analog input voltage) having a magnitude within a range of the ADC, and produces an n-bit digital output value indicative of the magnitude of the analog quantity. The range of the ADC extends from a minimum magnitude of the analog input quantity, represented by 0, to a full scale (FS) magnitude of the analog input quantity. Each bit of the n-bit binary output code produced by the typical ADC is a logic level ‘0’ when the magnitude of the input analog quantity is 0, and a logic level ‘1’ when the magnitude of the input analog quantity is the full scale magnitude.
As the magnitude of the input analog quantity increases from 0 to the full scale magnitude, the binary output code produced by the ADC increases. The resulting transfer function of the typical n-bit ADC resembles a flight of (2
n
−1) steps from a minimum binary output code to a maximum binary output code.
Unfortunately, the actual transfer function of an ADC may deviate from an ideal transfer function of the ADC due to any one of a number of error sources including offset error, gain error, and linearity error.
FIG. 1
is a graph of binary output code versus analog input voltage for a 3-bit analog-to-digital converter (ADC) receiving an analog input voltage, wherein an actual transfer function of the ADC deviates from an ideal transfer function due to offset error. As indicated in
FIG. 1
, offset error is the analog error by which a straight line drawn through centers of the steps of the actual transfer function fails to pass through 0.
FIG. 2
is a graph of binary output code versus analog input voltage for a 3-bit ADC receiving an analog input voltage, wherein an actual transfer function of the ADC deviates from an ideal transfer function due to gain error. As indicated in
FIG. 2
, gain error is a difference in slope between a first straight line passing through centers of steps of the actual transfer function and a second straight line passing through centers of steps of the ideal transfer function. Gain error is typically expressed as a percentage of the full scale magnitude of the analog input voltage.
Linearity errors result from ADC nonlinearities generally categorized as either “integral” nonlinearity (INL) or “differential” nonlinearity (DNL). INL is defined as a maximum deviation of an actual transfer function of an ADC from a straight line passing through the centers of the steps of the ideal transfer function of the ADC. DNL is defined as a maximum amount that a width of any step of the actual transfer function differs from an ideal step width of the ADC.
FIG. 3
is a graph of actual binary output codes produced by a 3-bit ADC and ideal binary output codes versus analog input voltage, wherein an actual transfer function of the ADC deviates from an ideal transfer function due to differential nonlinearity (DNL) in the actual transfer function of the ADC. In general, a width W
i
of the step corresponding to code i (i.e., a width W
i
of code i) of an n-bit ADC is ideally (FS/2
n
) where 1≦i≦(2
n
−2). The width W
i
of code i of the 3-bit ADC is thus ideally (FS/8) where 1≦i≦6. In
FIG. 3
, the width W
3
of code 3 is less than the ideal width (FS/8), and the width W
4
of code 4 is greater than the ideal width (FS/8). The differential nonlinearity of code 3, DNL
3
, is equal to W
3
−(FS/8), and is negative. The DNL of code 4, DNL
4
, is equal to W
4
−(FS/8), and is positive.
When an ADC is used in a measurement system, the above described error sources attributed to the ADC result in measurement errors. When an ADC is used in a control system, the above described error sources may result in the issuing of incorrect control signals. To reduce errors due to ADC error sources, it is known to add correction amounts to binary output codes produced by an ADC. For example, in the case of the 3-bit ADC of
FIG. 2
, code i produced by the 3-bit ADC may be “corrected” to (i—GAIN_ERROR(i)), where GAIN_ERROR(i) is the difference between the desired center of code i and the actual center of code i. Thus code 3 (binary code ‘011’) produced by the 3-bit ADC may be corrected to (3-0.6), and code 4 produced by the 3-bit ADC may be corrected to (4-0.8). Where GAIN_ERROR(i) has a fractional part, the corrected value requires a binary representation exceeding n bits. For example, code 3 (binary code ‘011’) produced by the 3-bit ADC may be corrected to 2.40 as described above. The binary representation of the corrected value 2.40 typically has an integer part ‘010’ preceding an implied decimal point and a fractional part ‘011 . . . ’ which follows the implied decimal point. Thus corrected code 3 is only fully represented by at least 6 bits instead of the original 3 bits ‘011’. To obtain a theoretically perfect correction, an infinite number of bits may be required. In practice a sufficient accuracy can be obtained with a limited number of bits which is greater than the number of bits in the original uncorrected binary data.
Many measurement and control systems are designed to receive only n bits from an n-bit ADC. It is often difficult to incorporate the above correction mechanism producing values having representations requiring greater than n bits into such systems. It would thus be desirable to have a system and method for correcting errors in an n-bit ADC which results in n-bit corrected output codes.
SUMMARY OF THE INVENTION
A method is disclosed for correcting output codes produced by an analog-to-digital converter (ADC), as is an apparatus embodying the method. The method includes receiving a digital output code i produced by the ADC, and randomly selecting a new digital output code within a range of code values dependent upon a difference between an actual code edge transition of the digital output code i and an ideal code edge transition of the digital output code i. An n-bit ADC produces digital output codes 0 through (2
n
−1). Digital output codes 1 through (2
n
−1) have actual and ideal code edge transitions as defined herein. The actual code edge transition of the digital output code i, where 1≦i≦(2
n
−1), is a transition between a digital output code i-1 and the digital output code i within an actual transfer function of the ADC, and the ideal code edge transition of the digital output code i is a transition between a digital output code i−1 and code i within an ideal transfer function of the ADC.
It is noted that when the ADC produces n-bit digital output codes, both the digital output code i and the new digital output code are n-bit values. Unlike other code correction approaches producing corrected output codes having more than n bits, the method, employing a probabilistic approach to ADC code correction, can be easily incorporated into measurement and control systems designed to receive only n bits from an n-bit ADC. It is also noted that the method corrects ADC output code errors resulting from a number of error sources, including offset error, gain error, and linearity error, or any combination thereof.
The new digital output code may be randomly selected within a range of code values dependent upon i, an edge nonlinearity (ENL) of the digital output code i, and an ENL of a digit
Conley Rose & Tayon PC
Hood Jeffrey C.
Jean-Pierre Peguy
Lauture Joseph
National Instruments Corporation
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