Nonvolatile semiconductor memory device

Details Nonvolatile semiconductor memory device Nonvolatile semiconductor memory device

2000-04-18

2001-02-13

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S210130

Reexamination Certificate

active

06188608

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device and more particularly relates to a nonvolatile semiconductor memory device like a flash memory including a differential sense amplifier.
Recently, a nonvolatile semiconductor memory device has been increasingly required to operate at higher and higher speeds. To meet such a demand, the application of a folded bit line arrangement, which is usually used for a dynamic random access memory (DRAM), has been proposed as an effective means for realizing such a high-speed operation. In the folded bit line arrangement, a bit line and its associated dummy bit line are connected in parallel to a sense amplifier. In this arrangement, reading is performed by comparing information stored in a memory cell connected to the bit line to reference information stored in an associated dummy cell connected to the dummy bit line and by amplifying a voltage difference therebetween. The arrangements of this type are disclosed in Japanese Laid-Open Publications Nos. 6-290591 and 8-203291, for example.
These folded bit line arrangements are superior to conventional opened bit line arrangements in terms of noise resistance and low power dissipation, and therefore applicable particularly effectively to circuits that should operate at higher speeds.
The present inventors analyzed the operation of a nonvolatile semiconductor memory device with the known folded bit line arrangement from various angles to find that the device of this type also has several shortcomings. Specifically, a device with the known folded bit line arrangement cannot read data from a desired memory cell accurately and rapidly enough, because there is capacitance imbalance between a bit line and its associated dummy bit line in reading out the data.
FIG. 7
illustrates a circuit configuration for a nonvolatile semiconductor memory device with the folded bit line arrangement as disclosed in Japanese Laid-Open Publication No. 8-203291 identified above. As shown in
FIG. 7
, the device includes sense amplifier
30
, bit line BL and its complementary bit line BLB. One end of the bit line BL is connected to the sense amplifier
30
via a transfer gate
33
, while the other end thereof is connected to a pre-charging transfer gate
11
P. One end of the complementary bit line BLB is connected to the sense amplifier
30
via a transfer gate
34
, while the other end thereof is connected to a pre-charging transfer gate
21
P. First and second memory cell blocks
110
a
and
120
a
are connected to the bit line BL and the complementary bit line BLB by way of first and second select gates
11
S and
22
S, respectively.
The first memory cell block
110
a
consists of four memory cells M
11
a,
M
12
a
, M
13
a
and M
14
a
, which are connected in series together and to word lines WL
1
a,
WL
2
a
, WL
3
a
and WL
4
a
, respectively. The second memory cell block
120
a
also consists of four memory cells M
21
a
, M
22
a
, M
23
a
and M
24
a
, which are connected in series together and also connected to the word lines WL
1
a,
WL
2
a
, WL
3
a
and WL
4
a
, respectively. Third and fourth memory cell blocks
110
b
and
120
b
with the same configurations as the first and second memory cell blocks
110
a
and
120
a
are connected to the bit line BL and the complementary bit line BLB via third and fourth select gates
12
S and
23
S, respectively.
Furthermore, a first dummy cell block
110
D with the same configuration as the first memory cell block
110
a
is connected to the bit line BL via a first dummy select gate
11
D. And a second dummy cell block
120
D with the same configuration as the first dummy cell block
110
D is connected to the complementary bit line BLB via a second dummy select gate
21
D.
Hereinafter, it will be briefly described how the nonvolatile semiconductor memory device with such an arrangement performs reading.
For example, suppose information should be read out from the memory cell M
14
b
in the third memory cell block
110
b.
In such a case, reference information (i.e., a reference potential) is supplied from the dummy cells M
21
D and M
22
D to the sense amplifier
30
. In the following example, the memory cell M
14
b
is now being written, i.e., the threshold voltage of the memory cell M
14
b
is between 1 and 2 V and the drain-source current thereof is about 80 &mgr;A. It should be noted that a memory cell is erased when a threshold voltage thereof is 8 V or more and the drain-source current thereof is 0 &mgr;A. On the other hand, the reference information stored in the dummy cells M
21
D and M
22
D, for example, is supposed to be average between a memory cell being erased and a memory cell being written.
First, the bit line BL and the complementary bit line BLB are pre-charged to a potential, which may be half of a supply potential V
DD
, by way of the pre-charging transfer gates
11
P and
21
P, respectively. Thereafter, the word line WL
4
b
connected to the control gate of the memory cell M
14
b
is activated and a high-level select signal SG
2
is applied to the gate of the third select gate
12
S to turn the gate
12
S ON. In this manner, the information is sent out from the memory cell
14
b
onto the bit line BL. In this case, capacitance caused by the third memory cell block
110
b
is applied to the bit line BL. At the same time, since the high-level select signal SG
2
also turns the second select gate
22
S ON, capacitance caused by the second memory cell block
120
a
is applied to the complementary bit line BLB.
On the other hand, the dummy cells M
21
D and M
22
D generate the reference potential to read the information from the memory cell M
14
b
. In this case, dummy word lines DWL
1
and DWL
2
connected to the respective control gates of the dummy cells M
21
D and M
22
D are activated and a high-level dummy select signal DSG
2
is applied to the gate of the second dummy select gate
21
D to turn the gate
21
D ON. In this manner, the reference information is transferred from the dummy cells M
21
D and M
22
D to the complementary bit line BLB. In this case, capacitance caused by the second dummy cell block
120
D is applied to the complementary bit line BLB by way of the second dummy select gate
21
D.
FIG. 8
schematically illustrates respective capacitance components applied to the bit line BL and the complementary bit line BLB while the semiconductor memory device shown in
FIG. 7
is reading data. In
FIG. 8
, the same members as those illustrated in
FIG. 7
are identified by the same reference numerals. As shown in
FIG. 8
, when a memory cell connected to the bit line BL is accessed, the sense amplifier
30
senses the line and diffusion capacitance CBL caused by the bit line BL and the capacitance C
110
b
caused by the third memory cell block
110
b
from the bit line BL. The sense amplifier
30
also senses the line and diffusion capacitance CBLB caused by the complementary bit line BLB, the capacitance C
120
a
caused by the second memory cell block
120
a
and the capacitance C
120
D caused by the second dummy cell block
120
D from the complementary bit line BLB. In this case, the capacitance C
110
b
or C
120
D includes the diffusion capacitance components of respective cells and the line capacitance caused by a sub-bit line when the drain of each cell is connected to the select gate.
As can be seen from
FIG. 8
, the capacitance applied to the bit line BL is different from that applied to the complementary bit line BLB during reading. For example, supposing each of the second and third memory cell blocks
120
a
and
110
b
and the second dummy cell block
120
D consists of the same number of memory cells, the capacitance CBL applied to the bit line BL is not greatly different from the capacitance CBLB applied to the complementary bit line BLB. Thus, extra load capacitance, i.e., the capacitance C
120
D caused by the dummy cell block
120
D, is applied to the complementary bit line BLB and seriously affects a read time.
In performing a readout operation using the differential sense ampl

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