Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1999-09-30
2001-10-09
Fahmy, Wael (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C428S429000, C428S700000, C428S911000, C428S919000
Reexamination Certificate
active
06300221
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to semiconductor devices and more particularly to reduced feature size devices and the fabrication of the same.
2. Description of Related Art
One goal of metal oxide semiconductor field effect transistor (MOSFET) scaling is to increase the density and speed of the integrated circuits in which such scaled-down devices are utilized. Devices are formed on a semiconductor substrate typically by depositing material and then patterning that material to remove specific portions on the wafer surface. Optical lithography has been used to pattern and generate device structures down to 0.2 micron (&mgr;m) geometry. As the minimum feature size continues to be scaled down to sub-0.10 &mgr;m, other techniques, such as electron-beam (E-beam) lithography, x-ray lithography, or extreme ultraviolet (EUV) lithography have been attempted. These latter lithography methods are generally expensive and have presented many technical barriers to widespread use.
As technologies shrink, it is increasingly difficult to obtain performance increases. Increasing device density typically means using devices with smaller channel lengths and widths. Increasing the speed of integrated circuits is generally accomplished by increasing the saturation drain current (I
Dsat
). Increasing the MOSFET I
Dsat
allows faster charging and discharging of parasitic capacitances. I
Dsat
is increased typically by either a decrease in the channel length or a decrease in the gate oxide thickness.
One factor that has generally not proved possible to scale is the transistor mobility. The electron and hole mobilities are a measure of the ease of carrier motion in a semiconductor crystal. In the semiconductor bulk, the carrier mobilities are typically determined by the amount of lattice scattering and ionized impurity scattering taking place inside the material. Carrier transport in the MOSFET, however, primarily occurs in the surface inversion layer. In small feature size devices, the mobility due to the gate-induced electric field (i.e., transverse electric field) and drain-induced electric field (i.e., longitudinal electric field) act on the carriers and significantly influence the velocity of the moving carriers in the inversion layer of a device channel. The drain-induced electric field acts to accelerate the carriers parallel to the semiconductor-gate oxide (e.g., Si-SiO
2
) interface, whereupon the carrier suffers scattering similar to as in the bulk. The gate-induced electric field, however, also causes the carriers to be accelerated toward the semiconductor-gate oxide (e.g., Si-SiO
2
) surface. Thus, the carriers near the surface experience additional motion-impeding collisions with the semiconductor surface. As a result, the carrier mobility at the surface is observed to be lower than in the bulk. These and other scattering mechanisms cause the mobility to saturate at what is referred to as velocity saturation. Velocity saturation prevents increases in mobility expected from decreases in gate length.
What is needed is a method of improving mobility in transistor devices.
SUMMARY OF THE INVENTION
A method is disclosed. The method includes forming a spacer mask having a defined edge over a first portion of a substrate, and alternatively conformally depositing over a second portion of a substrate including the spacer mask a predetermined number of layers of at least a first material and a second material. In one aspect, the first material and the second material have a different etch rate for a predetermined etchant. The method also includes forming a free-standing spacer comprising the first material and the second material, having a width equivalent to the thickness of one of a layer of the first material and a layer of the second material.
REFERENCES:
patent: 6110790 (2000-08-01), Chen
Cheng Peng
Doyle Brian S.
Roberds Brian E.
Blakely , Sokoloff, Taylor & Zafman LLP
Brewster William M.
Fahmy Wael
Intel Corporation
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