Television – Synchronization
Reexamination Certificate
1998-12-17
2001-10-02
Eisenzopf, Reinhard J. (Department: 2614)
Television
Synchronization
C348S536000, C348S537000, C358S461000
Reexamination Certificate
active
06297849
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to an output timebase corrector as defined in the precharacterizing part of claim
1
, and to a display device comprising such an output timebase corrector as defined in the precharacterizing part of claim
8
. The invention also relates to an output timebase correction method as defined in the precharacterizing part of claim
7
.
U.S. Pat. 5,150,201 discloses a digital television signal-processing circuit with an analog-to-digital converter (further referred to as A/D converter), a color decoder, a skew filter controlled by a phase-locked loop (further referred to as PLL), a signal processor, a dual-port memory controlled by a clock-phase shifter, and a digital to analog converter (further referred to as D/A converter).
The A/D converter supplies a digitized video signal to the color decoder. The color decoder supplies two color difference signals and a luminance signal to the skew filter. The PLL receives a synchronizing signal present in the digitized video signal, and supplies a control signal to the skew filter. The skew filter supplies orthogonal sampled input video signals to the signal processor to facilitate simple video processing, for example filtering. The signal processor supplies orthogonal sampled output video signals to the dual-port memory. The dual-port memory supplies delayed output video signals to the D/A converter to obtain analog video signals to be supplied to a display device. The A/D converter, the color decoder, the skew filter and an input part of the dual-port memory are clocked with the same first clock signal.
The clock-phase shifter receives the first clock signal and a line flyback signal indicating a timing of a line deflection of the display device to supply a second clock signal to an output part of the dual-port memory and the D/A converter. The second clock is derived from the first clock signal by a clock-phase shifter. In such a clock-phase shifter, the first clock signal enters a chain of delay stages whose overall delay is approximately equal to the period of the first clock signal. The taps of all delay stages are connected to associated locking stages which are locked by applying the line flyback signal. The stored phase value can be obtained from the locking stages as a thermometer code specifying the number of delay stages required to delay the first clock signal.
The dual-port memory converts the orthogonal sampled (with the first clock signal) output video signals into delayed output video samples synchronously with the second clock signal. The delay is controlled by the flyback signal.
It is a drawback of the prior-art that two clocks are needed. Although the two clocks have the same frequency, the phases differ dynamically, thereby causing interference. It is also a drawback of the prior-art that the clock-phase shifter is a very delicate analog circuit having a design which depends on the IC process. Moreover, a calibration of the delays is needed as the analog delays vary with temperature, supply voltage and process spread. Due to the two asynchronous clocks, simulations of the prior-art circuit have to be performed with analog simulators, which is a complication.
BRIEF SUMMARY OF THE INVENTION
It is an object of the invention to provide an output timebase corrector which obviates the prior-art drawbacks.
To this end, a first aspect of the invention provides an output time base corrector as defined in claim
1
. A second aspect of the invention provides an output timebase correction method as defined in claim
7
. A third aspect of the invention provides a display device with an output time base corrector as defined in claim
8
. Advantageous embodiments of the invention are defined in the dependent claims.
The output time base corrector receives orthogonal sampled video samples. The orthogonal video samples may be generated by a time-discrete video processor. This video processor receives and supplies orthogonal sampled video samples to facilitate easy processing (for example, one or multi-dimensional filtering) of the video samples in the video processor. The output time base corrector comprises a time-discrete sample rate converter which receives the orthogonal sampled video samples and is controlled by a control signal to supply asynchronous sampled video samples to a display device via a D/A converter. The time-discrete video processor, the sample rate converter, and the D/A converter are clocked with a clock signal which represents clock instants and is generated by one and the same clock generator. The clock generator may generate the clock signal with a very stable frequency by using a crystal.
A discrete time oscillator of a time-discrete phase-locked loop generates the control signal of the sample rate converter as a time base signal which is locked to reference instants related to line positions on a raster-scanned display screen of the display device. The reference instants may be line flyback pulses occurring in a line deflection circuit which generates a line deflection current through a line deflection coil around a cathode ray tube.
The output time base corrector according to the invention converts orthogonal sampled video into a line-locked video which, after low pass filtering, is locked to the reference instants. In the output time base corrector according to the invention, the orthogonal sampled video is clocked with a clock signal which is not locked to the reference instants. That is why the line-locked video is also referred to as asynchronous sampled video samples. The sample values occurring at the clock instants of the clock signal have to be interpolated from the orthogonal sampled video by the sample rate converter. Consequently, the time-discrete phase-locked loop controls the sample rate converter in such a way that the video values occur in the correct position on the display screen.
In the output time base corrector according to the invention, all circuits are clocked by clock signals originating from one and the same clock generator. In principle, the clock generator generates one clock signal. However, it is possible to supply clock frequencies to the different circuits of the output time base corrector, which clock frequencies are an integral multiple of each other and all of which have the same phase. No interference will occur due to different clock-phases, no analog circuits are involved, and the circuit can be simulated with a digital simulator.
In an embodiment as defined in claim
2
, a waveform generator receives the time base signal to supply the control signal to the sample rate converter. The control signal is the time base signal adapted in accordance with a desired waveform. The waveform is selected to compensate for a non-constant deflection rate of the electron beam on the display screen. The non-constant deflection rate occurs if expensive measures in the deflection circuitry to obtain a constant deflection rate across the entire screen are not applied (for example, an east-west correction, or when a linearity coil has been omitted). In this way, the imperfections in the deflection are corrected by signal-processing which is cheap and reliable.
In an embodiment as defined in claim
3
, the discrete time oscillator integrates an incremental value at every clock instant to generate a periodical time-discrete saw-tooth signal which restarts at a certain start value after a predetermined period of time. The time base signal is locked to the reference instants by controlling the predetermined period of time of the periodical time base signal, dependent on a difference value between a selected reference value and a value of the time base signal at the reference instants. The time base signal restarts at the certain start value (or pre-set value) after the difference value at the reference instant has been determined. The repetition period of the time base signal may be controlled by adapting the increment value or a flyback value. The flyback value is the difference between the last sample value of the time base signal in a certain
Nillesen Antonius H. H. J.
Stessen Jeroen H. C. J.
Eisenzopf Reinhard J.
Tran Trang U.
U.S. Philips Corporation
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