Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
2000-04-11
2001-12-04
Pascal, Robert (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S261000, C330S051000
Reexamination Certificate
active
06326846
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to differential amplifiers and in particular to FET differential amplifiers capable of providing good performance at reduced supply voltages.
DESCRIPTION OF RELATED ART
Many data conversion circuits, including Analog-To-Digital Converters and Digital-To-Analog Converters, operate utilizing comparator circuitry which includes fully differential amplifiers.
FIG. 1
is a diagram of a conventional fully differential comparator circuit which provides a comparator output Out indicative of the relative magnitude of an analog input having a positive component IN+ and a negative component IN− and a reference having a positive component REF+ and a negative component REF−.
The
FIG. 1
comparator circuit including two fully differential amplifiers A
1
and A
2
which drive a regenerative latch circuit B
1
.
FIGS. 2A
,
2
B,
2
C,
2
D and
2
E are timing diagrams of timing signals Clk, R, I, M and C, respectively, for controlling operation of the
FIG. 1
comparator circuit. When signal Clk is high, timing signal R (
FIG. 2B
) is active so that the switches associated with signal R will be turned on. This will cause the inverting input and the non-inverting input of each amplifier A
1
and A
2
to be connected directly to the non-Attorney inverting and inverting output, respectively, of each amplifier. This causes the closed loop gain of amplifiers A
1
and A
2
to be unity, with the amplifier inputs (and outputs) being at the threshold voltage of each amplifier. In addition, signal R will short the inputs of latch circuit B
1
together.
Timing signal I (
FIG. 2C
) is also active when Clk is high so that the negative component of the differential analog signal being compared, IN−, is coupled to input capacitor C
1
and the positive component IN+ is coupled to input capacitor C
2
. At this point, capacitors C
1
and C
2
have a stored voltage that corresponds to the magnitude of the analog inputs IN− and IN+. Capacitors C
3
and C
4
will have a stored voltage that corresponds to the magnitude of the difference between threshold voltages of amplifiers A
1
and A
2
.
When clock Clk goes low, signals R and I go inactive followed by signal M going active. Among other things, this causes the switches shorting the amplifier inputs to the outputs to open. The amplifiers A
1
and A
2
are thus operating open loop. In addition, input capacitor C
1
is coupled to reference voltage Ref− and input capacitor C
2
is coupled to reference voltage component Ref+. Thus, the change in voltage at the inverting input of amplifier A
1
will be the difference between the magnitude of reference voltage Ref− and input IN− and the change in voltage at the non-inverting input will be the difference in magnitude of reference voltage Ref+ and IN+.
The differences will be amplified by amplifier A
1
, with the output being proportional to the difference between input IN+/IN− and Ref+/Ref−. Amplifier A
2
functions to amplify the difference voltage further. Finally, just as clock Clk goes high, and before signals R and I become active again, signal C goes active thereby latching the difference voltage presented at the inputs of the latch circuit B
1
. The digital output of latch circuit B
1
will be either a “1”, or a “0” depending upon the relative magnitudes of IN+/IN− and Ref+/Ref−.
The gain of the differential amplifiers A
1
and A
2
are each typically 5-20. The gain of these cascaded amplifiers operate to reduce the input-referred offset voltage arising from the device mismatch in regenerative latch circuit B
1
.
FIG. 3
shows a typical implementation of a prior art differential amplifier together with the NMOS reset switches which connect the inputs and outputs together. The amplifier circuit includes differential input NMOS transistors
12
A and
12
B connected to a tail current source which includes NMOS transistor
10
. Diode-connected PMOS transistors
14
A and
14
B form the load circuit, with NMOS transistors
16
A and
16
B forming the reset switches.
The open-loop gain of the
FIG. 3
amplifier is approximately equal to the ratio of the transconductance (gm) of the NMOS input transistors
12
A/
12
B to the transconductance of the PMOS load transistors. Thus, the gain can be expressed as follows:
G=gm
I/gm
L
(1)
where G is the amplifier gain, gm
I
is the transconductance of the input transistors
12
A/
12
B and gm
L
is the transconductance of the load transistors
14
A/
14
B.
Since transistors
12
A/
12
B and
14
A/
14
B all operate in the saturation region, the transconductance of these transistors can be expressed as follows:
gm=2I
DS
/(V
GS
−V
t
) (2)
where I
DS
is the drain-source current, V
GS
is the gate-source voltage and V
t
is the transistor threshold voltage.
Combining equations (1) and (2), the amplifier gain can be expressed as follows:
G =(V
GSL
−V
tL
)/(V
GSI
−V
tI
) (3)
where V
GSL
and V
GSI
are the gate-source voltage of transistors
14
A/
14
B and
12
A/
12
B, respectively, and v
tL
and V
tI
are the threshold voltages of transistors
14
A/
14
B and
12
A/
12
B, respectively.
The numerator and denominator of equation (3) are each sometimes referred to as the gate drive voltage, that is, the degree to which the gate-source voltage exceeds the threshold voltage. The gain G can be considered to be approximately equal to the ratio of the gate drive voltage of the load transistors
14
A/
14
B to the gate drive voltage of the input transistors
12
A/
12
B.
In a typical configuration, the gate drive voltage of the input transistors
12
A and
12
B has a practical minimum value of 150-200 mV in order to preserve a reasonable input capacitance. The maximum gate drive of the load transistors
14
A and
14
B is limited by the magnitude of the supply voltage VDD. A supply voltage VDD of +5 volts typically supports a gain of about 7-10 for the
FIG. 3
circuit.
For CMOS processes where the magnitude of the threshold voltage Vt for the NMOS and PMOS transistors is about 0.75 volts, the
FIG. 3
amplifier topology is unsuitable for operation at significantly lower supply voltages VDD, such as +2.7 volts. There is a need for an amplifier design that is suitable for comparator circuit and other applications capable of operating at reduced supply voltages. As will become apparent to those skilled in the art upon a reading of the following Detailed Description of the Invention together with the drawings, the present invention addresses this shortcoming of the prior art by providing an amplifier capable of good performance at reduced supply voltages.
SUMMARY OF THE INVENTION
A differential amplifier and related method are disclosed. The amplifier includes first and second MOS transistors, typically NMOS transistors, having their respective sources coupled to a tail current source. The gates of the first and second MOS transistors function as the differential input to the amplifier.
Third and fourth MOS transistors, typically PMOS transistors, are connected as loads, with the third load transistor and the first input transistor having their respective drain-source paths connected in series to form a first current path and with the fourth load transistor and the second input transistor having their respective drain-source paths connected in series to form a second current path. Biasing circuitry is provided to cause the load transistors to operate in the linear region of operation as opposed to the saturation region of operation. This feature increases the gain of the amplifier at low voltage operation.
REFERENCES:
patent: 4710724 (1987-12-01), Connell et al.
patent: 4785259 (1988-11-01), Seelbach et al.
patent: 5021745 (1991-06-01), Kondou et al.
patent: 5936466 (1999-08-01), Andoh et al.
Choe Henry
Girard & Equitz LLP
National Semiconductor Corporation
Pascal Robert
LandOfFree
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