Data processing: artificial intelligence – Neural network
Reexamination Certificate
1999-02-11
2001-12-18
Powell, Mark R. (Department: 2122)
Data processing: artificial intelligence
Neural network
C706S014000, C706S026000, C706S027000
Reexamination Certificate
active
06332137
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to computer and artificial intelligence recognition systems, and more particularly to combinations of field programmable logic devices and zero instruction set computers that allow recognition jobs and lesson libraries to be changed on-the-fly.
DESCRIPTION OF THE PRIOR ART
A zero instruction set computer (ZISC) chip based on neural networks was developed by IBM in Paris and the present inventor, Guy Paillet. The first generation ZISC chip has thirty-six independent neurons or parallel processors. Each cell includes sixty-four bytes storage, a distance evaluator and a category register. Vectors that enter the chip are broadcast to all the cells for evaluation of the distance, or similarity, between the incoming vector and stored vectors. If the input and stored vectors match, or are similar, the category or attribute register will output to the response bus. Each of these cells is designed to compare an input vector of up to sixty-four bytes with a similar vector stored in the cell's memory. If the input vector matches the vector in the memory near enough, the neuron cell “fires” its output. Otherwise, it doesn't. All thirty-six cells in a ZISC chip compare their memory to the input vector at the same time. The cells that had a match are identified at the output. The ZISC will learn new vectors and adapt to the collection of reference vectors by submitting the training vector along with the desired output. No programming is required to teach the network. Save and restore operations allow transfer to and from the host computer.
In prior art recognition systems, a serial approach is universally used for pattern matching, e.g., a computer program loads a pattern into a memory, then fetches stored patterns from a large array, and then compares them one at a time looking for matches. More patterns to check means more time is needed to do the checking. Very fast computers can check lots of patterns in a short time, but eventually, a limit is reached in how many patterns can be realistically processed. A ZISC network, such as one comprised of ZISC036 devices, matches all the patterns in memory with the input at one time. The number of patterns in memory can be expanded by adding more such devices, and without suffering a decrease in recognition speed. Conventional ZISC chips have been used to offload the recognition function from general-purpose computers in various applications.
Age Eide, et al., describe the problem of facial recognition using the IBM ZISC036 chip in, “Eye Identification for Face Recognition with Neural Networks”, presented at the SPIE Conference at Orlando, Fla., April 1966. A preprocessor for doing wavelet transforms upstream of the IBM ZISC036 RBF-chip is used to increase processing speed. Another implementation discussed is a two-stage neural network implemented in software. The first stage was used to recognize the common properties, and the second stage was used to recognize the differences.
The prior art in recognition systems has tended to focus on one media, such as video or audio. And if any preprocessors were used to improve the performance of the neural networks, such were fixed or inflexible in order to get portability. When size and expense were no object, then too much reliance on software has been placed and resulted in expensive and non-portable appliances.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a recognition system that preprocesses several different media inputs for application as a single vector to an easily expandable array of neural networks.
It is a further object of the present invention to provide a recognition system that enables the field reprogrammability of its media preprocessors.
Briefly, a recognition system embodiment of the present invention comprises at least two field-programmable logic array devices connected to a common vector-input port of an array of a zero-instruction-set computer. Each field-programmable logic array device is configured to preprocess data from different respective media. Neural networks within the zero-instruction-set computer recognize the input patterns by comparing in parallel their vectors with those stored in each neural network cell. A variety of recognition jobs are made possible by changing the programming on-the-fly of the field-programmable logic array devices to suit each new job.
An advantage of the present invention is that a recognition system is provided that can be adapted on-the-fly to handle different recognition jobs.
Another advantage of the present invention is that a recognition system is provided that is easy to expand and that can simultaneously depend on several input media to quickly find pattern matches.
Another advantage of the present invention is that a recognition system is provided in a camera system that can process realtime images without software delay and slow down.
These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.
REFERENCES:
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Duranton, M., Image processing by neural networks, IEEE Micro, vol.: 16 Issue: 5, Oct. 1996, pp.: 12-19.*
Age Eide, et al., “Eye Identification for Face Recognition with Neural Networks”, SPIE Conference, Orlando, FL, Apr. 1966.
Age Eide, et al., “The IBM ZISC036 Zero Instruction Set Computer”, Ostfold College, Halden, Norway, 1996.
Ghislain de Tremiolles, et al., “Visual Probe Mark Inspection, Using Hardware Implementation Of Artificial Neural Networks, in VLSI Production”, IWANN, Lanzarote, Canary Islands, Spain, Jun. 1997.
Hori Toshikazu
Paillet Guy
Woo Jeffrey M.
Law Offices of Thomas E. Schatzel
Powell Mark R.
Schatzel Thomas E.
Starks, Jr. Wilbert L.
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