Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1998-11-30
2001-10-16
Metjahic, Safet (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S758010, C324S754090
Reexamination Certificate
active
06304095
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to a semiconductor measurement instrument capable of dynamically changing examination criteria. In particular, the invention relates to a semiconductor measurement instrument capable of dynamically changing examination criteria used in semiconductor parametric test systems which measure semiconductor parameters on a wafer and evaluate whether a test has been passed or failed, evaluate properties, etc.
BACKGROUND OF THE INVENTION
Wafer testing during production of semiconductor circuit elements is one use of semiconductor parametric testers. An example of a semiconductor parametric tester used for this purpose will be described while referring to FIG.
1
. Semiconductor parametric test system
1
has a tester unit
3
which feeds electrical signals to wafer
2
serving as the object to be measured and measures the electrical signals from wafer
2
. Test system
1
also has a prober
5
which takes wafer
2
from wafer lot
4
and brings a probe into contact with a specific die. Computer
6
A controls tester unit
3
and prober
5
and processes the measurement data. Measurement program
6
B operates computer
6
A.
Measurement program
6
B has a test plan
7
, which consists of a specification for wafer
2
and the devices on the wafer, etc.; a measurement algorithm
8
which consists of files that define the measurement algorithm; core program
9
which initiates each part and loads and executes test plan
7
and measurement algorithm
8
, etc.; and a limit file
10
. Moreover, measurement program
6
B includes user interface program
9
a
, through which data is input from and output to an operator via a display and a keyboard.
Test plan
7
, measurement algorithm
8
, and limit file
10
each have, for instance, a fill-in-the-box builder
7
e
,
8
c
,
10
a
, respectively so that the user can easily construct files.
Test plan
7
includes wafer spec
7
a
which defines the name, location, and other attributes of the dies on a wafer; a die spec
7
b
which defines the name and location of the modules on the dies; a probe spec
7
c
, which defines the pin connections between the device pad of the probe card and the switching matrix; and a test spec
7
d
, which defines the measurement algorithms used to test the device.
Hereafter is defined the terminology used in the present specification and in reference to FIG.
2
. The wafers
20
includes a set of several dies
22
, with several dies
22
defining one wafer, the dies
22
include a set of modules
24
, with several modules
24
defining one die
22
. The modules
24
include are a set of devices
26
and are the largest unit that can be programmed at a time. The devices
26
are the units on the module
24
, such as a resistor, MOSFET, transistor, etc. Moreover, a wafer lot is a set of wafers
20
and is the unit that can be submitted to a prober
5
at one time.
Referring to
FIG. 3
, test spec
7
d
defines the measurement algorithm
8
to be used in testing a device
26
. Basically, the test spec
7
d
defines the device
26
to be measured, the name of the measurement algorithm
8
, the number
30
of the pad to be connected to the device terminal, the input variable
32
for the argument of each measurement algorithm
8
, the returned value (measurement result) for each measurement algorithm
8
, the output variable
36
for each binning limit, etc.
Here, binning is a block where the numbers associated with the measurements have been segregated between certain values and values that define a block are called the limits. Binning is used to define a range when evaluating whether or not a measurement fails to meet the value that the user expects; to statistically analyze the measurement results for evaluation of the properties of the object being measured and for evaluation of the production processes; to define a range when evaluating whether the measurements are valid or invalid; etc. The limits are written in limit file
10
in FIG.
1
and are incorporated into test spec
7
d.
Measurement algorithm
8
determines the order in which semiconductor parameter tests are executed, the device parameters are extracted, etc., and includes algorithm spec
8
a
and algorithm library
8
b
. Algorithm spec
8
a
defines specifications, including the input variable, output variable, device variable, name of the device terminal, etc., for each measurement algorithm. Algorithm library
8
b
is constructed from subprograms that use the individual algorithm functions.
The above described device is an example of a conventional semiconductor parametric test system. However, that system does have problems. Those problems will be described while referring to the test flow chart in FIG.
8
.
When a wafer is tested by conventional test system
1
, the wafer lot is set on the prober (
81
a
) and the wafer on the prober is selected (
81
b
). The test shell (core program) is started (
82
a
), the test plan is selected (
82
b
) and the limit file is selected (
82
c
). Thus, it is now possible to test the wafer, and once the wafer is loaded (
81
c
), the test is started (
82
).
The dies arranged on the wafer are measured (
83
) in accordance with a specific order that has been determined by the test plan. The system evaluates whether the wafer passes or fails and whether the measurements are valid or invalid using the binning from the limit file that was selected in
82
c
(
84
). These data are then recorded in the computer memory (
85
). The program determines whether there are any dies remaining once it completes the measurements of one die (
86
) and this measurement process is repeated until the measurements of the objects to be measured on the wafer have all been completed.
However, the limits are determined by the user and therefore, there are cases where these limits are not necessarily the optimum limits and changes based on measurement results become necessary. In this case, the test must first be stopped, the wafer is unloaded, as shown in step
87
, and then a different limit file must be read in order to change the limits. As a result, for instance, limit file B is incorporated into the test plan and re-testing is performed based on this file, as shown in FIG.
3
.
This re-running of measurements takes time and has an effect on throughput of the semiconductor circuit production process. Moreover, it also increases cost when re-running of measurements is performed by an operator. Therefore, there is a need for a system with a flexible test plan that allows for monitoring the measurement results as a test is being performed and for automatic changing of the examination criteria without stopping the test.
An object of the invention is to provide a test system wherein criteria for evaluating whether a test is passed or failed can be changed without stopping the test, by changing the limits automatically, or by operator request.
SUMMARY OF THE INVENTION
The present invention is a semiconductor measurement instrument that is capable of dynamically changing its examination criteria. In particular, the invention is a semiconductor measurement instrument that is capable of dynamically changing criteria for evaluating whether a test is passed or failed. The invention can be used in semiconductor parametric test systems that measure parameters of semiconductors on a wafer and evaluate whether the test is passed or failed, that evaluate properties, etc., during semiconductor integrated circuit production process, etc.
This characteristic is realized by a function that enables the contents of a limit file that have been written to be changed as the test is being executed. In order to make this function easy to use, the invention has a structure wherein the binning, which can be freely designed by the user, is recorded in one limit file and the criteria for evaluating whether the test is passed or failed and the range of valid measurements are selected from several user binnings.
REFERENCES:
patent: 5495578 (1996-02-01), Rohrbaugh et al.
patent: 5793650 (1998-08-01), Mizra
HP Specs User&apo
Agilent Technologie,s Inc.
Hollington Jermele M.
Metjahic Safet
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