Static information storage and retrieval – Format or disposition of elements
Reexamination Certificate
1998-06-30
2001-02-13
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Format or disposition of elements
C365S063000, C365S230030, C361S760000, C361S761000, C361S764000
Reexamination Certificate
active
06188595
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to integrated circuit memories and particularly, but not by way of limitation, to a memory architecture and addressing for optimized storage density in an integrated circuit package or on a circuit board.
BACKGROUND OF THE INVENTION
Computer systems, communications systems, and other electronic devices often utilize integrated circuit memories for storing data. For example, dynamic random access memories (DRAMs) provide dense solid-state data storage that is quickly accessed for reading or writing. DRAMs are a volatile form of memory; stored data is lost when power is removed. DRAMs also must typically be refreshed in order to maintain the stored data. In another example, static random access memories (SRAMs) provide volatile data storage that avoids any periodic refresh requirement. “Flash” and other electrically erasable and programmable read-only memories (EEPROMs) provide nonvolatile data storage; stored data is maintained when power is removed. Access and programming times may be longer for EEPROMs than for DRAMs. Other types of commercial memory integrated circuits are also available.
Many applications require large amounts of memory capacity in order to meet data storage requirements. For many such applications, several memory integrated circuits are each individually disposed in an integrated circuit package, and the packages are mounted on a printed circuit board. The printed circuit board is then plugged into an available slot in the computer system or other electronic device such that a microprocessor can access the memory integrated circuits for storing and retrieving data. For applications requiring even larger amounts of memory capacity, several such printed circuit boards carrying memory integrated circuits are plugged into available slots for use by the computer system or other electronic device.
Modem computer systems, communications systems, and other electronic devices demand a high degree of functionality in a minimum volume, for portability and other reasons. Moreover, the electronics industry often uses standardized integrated circuit packages, so that system designers can design and build a computer system using standard components. Because the “footprint” of a standardized integrated circuit package (i.e., its size, connection locations, etc.) is known, the system designer can design the other portions of the computer system assuming a standard integrated circuit package. Thus, a computer system can be designed even before the design of the actual memory integrated circuits carried within the standard integrated circuit package. Such flexibility is particularly important in the computer industry, in which product design cycles are extremely short. Products not timely introduced with the maximum available functionality may not be marketable. Thus, there is a strong need for electronics products that are designed with standardized integrated circuit packages, but which offer maximum functionality while occupying a minimum volume.
SUMMARY OF THE INVENTION
The present invention provides, among other things, an integrated circuit (IC) architecture that optimizes memory storage density, such as for a particular size of standard IC package. This increases memory density per unit volume and advantageously allows design of a computer, communication, or other electronic system using standard IC packages while the memory IC is concurrently being designed. This enables timely introduction of high storage density products onto a highly competitive electronics market.
In one embodiment, the invention provides, among other things, an apparatus including a memory integrated circuit (IC), and an IC carrier. The memory IC includes a plurality of N memory blocks arranged in a row in a first dimension, wherein log
2
(N) is a noninteger. The memory blocks include a block size B
1
in the first dimension. Each memory block include a plurality of memory cells. The IC carrier includes an area carrying the memory IC. The area includes a size C
1
in the first dimension, and the memory IC includes a die size D
1
in the first dimension, wherein (C
1
−D
1
) is approximately less than B
1
. In one embodiment, the apparatus also includes a computer system including a processor communicatively coupled to the memory IC. In a further embodiment, the apparatus also includes a plurality of the memory ICs, a memory controller coupled to the memory ICs, and a processor coupled to the memory controller.
Another aspect of the invention provides, among other things, an apparatus that includes a plurality of X memory ICs. Each memory IC includes Y directly addressable storage locations, wherein log
2
(Y) is a noninteger. The apparatus also includes a memory controller. The memory controller decodes A address inputs into (X)(Y) addresses, leaving (2)
A
−{(X)(Y)} addresses unused. In one embodiment, each memory IC includes a chip select input and a plurality of other memory cell address inputs. Data is accessed on a particular one of the memory ICs only when the chip select input is active. The memory controller is independently coupled to each chip select input, selecting between the chip select inputs by decoding a number Z of the A address inputs, wherein Z>log
2
(X). In one embodiment, using memory ICs having some memory cells that are not functional, the addressing is used to decode Y directly addressable functional storage locations, wherein log
2
(Y) is a noninteger.
Another aspect of the invention provides, among other things, a method that includes forming an integrated circuit (IC). The IC includes a plurality of N memory blocks arranged in a row in a first dimension, wherein log
2
(N) is a noninteger. The memory IC has a die size D
1
in the first dimension. The memory blocks include a block size B
1
in the first dimension. Each memory block including a plurality of memory cells. The method also includes disposing the memory IC on an area of an IC carrier. The area has a size C
1
in the first dimension, wherein (C
1
−D
1
) is approximately less than B
1
.
The present invention minimizes space wasted by putting a too-small memory IC in a particular standard IC package. Instead, the number of memory blocks is increased such that the memory die size uses more of the available space, providing correspondingly more storage capacity. Many applications exist for the present invention. For example, the packaged memory ICs can be arranged on a printed circuit board (PCB), such as a Personal Computer Memory Card International Association (PCMCIA) card, providing a removable, high density, high capacity, credit-card size nonvolatile flash memory for laptop computers or other applications. These and other advantages will become apparent upon reading the following detailed description of the invention and viewing the accompanying drawings.
REFERENCES:
patent: 5680342 (1997-10-01), Frankeny
patent: 5936877 (1999-08-01), Morgan et al.
patent: 5953215 (1999-09-01), Karabatsos
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
Tran Andrew Q.
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