Compensation of timing errors caused by dynamic thermal...

Details Compensation of timing errors caused by dynamic thermal... Compensation of timing errors caused by dynamic thermal...

1999-12-02

2001-11-13

Pascal, Robert (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including temperature compensation means

C330S256000

Reexamination Certificate

active

06317001

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to the compensation of a change in timing information caused by thermal variations, and in particular relates to differential amplifiers.
Most electronic circuits appear to be sensitive on thermal variations caused mainly by variations in ambient temperature or by dynamic behavior due to power consumption. In particular, different thermal variations at different locations of electronic circuits often lead to an unwanted behavior of the circuit.
In digital systems, information is mainly transmitted or processed by means of signals changing from one state to another. Timing information comprises the information about when a signal is due to change. A digital circuit, which is processing or transmitting timing information, generates a sequence of output state transitions as a result of a sequence of input state transitions. The relationship between timing information of input transitions must be reflected at the output of the system. Furthermore, the time elapsing between input state changes should also elapse between output state changes caused by their respective input state changes. Otherwise, the system has changed the timing information, which should be avoided in most applications.
UK-A-2316559 discloses a temperature compensated driver circuit that is relatively stabilized in waveform amplitude and output timing by detecting the power consumption of its output driver stage and correcting and controlling the power consumption. A temperature detector detects the temperature changes of output elements and a temperature compensator adjusts the timing of an output signal against an input signal in response to a temperature-detecting signal from the temperature detector. This, in particular, allows compensating timing deviations due to a temperature-induced variation of a pulse delay time.
In digital circuits, it has been observed that thermal variations can lead to a timing drift dependent on the duty cycle as the ratio of the sum of all pulse durations to the total period. Most conventional circuits are therefore designed to provide a good thermal coupling between corresponding components which has been shown to reduce this so-called duty cycle drift, i.e. the variation of the propagation delay dependent on the duty cycle, from e.g. 2 ns to 0.5 ns. In modern digital applications, however, thermal coupling has proved not to be sufficient to reduce the duty cycle drift e.g . down to values of 100 ps or smaller. Furthermore, for physical reasons it is clear that an ideal thermal coupling will never be possible, so that thermal coupling, even if significantly improved, will always have a natural limitation.
As apparent from the above said, it is clear that a timing information, such as the duty cycle drift or variations in the delay time as explained in GB-A-2316559, can be changed by thermal variations.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an improved compensation of thermal variations, preferably for maintaining timing information in digital systems unchanged. This object is solved by the independent claims. Preferred embodiments are shown by the dependent claims.
For a better understanding of the compensation of thermal effects as carried out by the invention, a new theoretical model explaining the effect of thermal variations shall be developed. This model will be illustrated for the example of a differential amplifier as depicted in
FIG. 1
which is well-known in the art, with fixed input and output levels, as used e.g. in digital circuits.
The differential amplifier receives differential input signals IN and NIN and provides differential outputs OUT and NOUT. The signal NIN represents the complement to the signal IN and, accordingly, the signal NOUT represents the complement to the signal OUT. The constitution and functioning of differential amplifiers is well known in the art and needs not to be explained herein in detail.
In the example of
FIG. 1
, the differential amplifier is built up of two NPN transistors Q
1
and Q
2
with common emitters coupled to a current source I
1
. The input signals IN and NIN are respectively coupled to the base of the transistors Q
1
and Q
2
. The collectors of the transistors Q
1
and Q
2
are coupled via impedances R to a source of high potential VCC and respectively represent the output signals OUT and NOUT.
In a logical ‘low’ state (i.e. when IN=low and NIN=high), the transistor Q
1
is off so that the power dissipation Pd1_lo of the transistor Q
1
is zero. Transistor Q
2
is on, leading to a power dissipation Pd2_lo of the transistor Q
2
with:
Pd2_lo
=
I1
·
VCE2_lo
=
I1
·
(
VCC
-
R
·
I1
-
VE
)
=
I1
·
(
VCC
-
R
·
I1
-
(
Vnin_lo
-
VBE2
)
)
whereby VCE2_lo represents the collector-emitter voltage of transistor Q
2
and VE represents the voltage at the coupled emitters. Vnin_lo is the voltage at the base of transistor Q
2
and substantially represents the logic ‘high’ potential, and VBE2 is the base-emitter voltage of transistor Q
2
.
In a logical ‘high’ state (with IN=high and NIN=low), transistor Q
1
is on, leading to a power dissipation Pd1_hi thereof with:
Pd1_hi
=
I1
·
VCE1_hi
=
I1
⁡
(
VCC
-
R
·
I1
)
=
I1
⁡
(
VCC
-
R
·
I1
-
(
V
⁢
 
⁢
in_hi
-
VBE1
)
)
wherein VCE1 represents the collector-emitter voltage of transistor Q
1
. Vin_hi is the voltage at the base of transistor Q
1
and substantially represents the logic ‘high’ potential, and VBE1 is the base-emitter voltage of transistor Q
1
. Since the transistor Q
2
is turned off, the power dissipation Pd2_hi is zero.
Assuming that the applied logic potential are substantially equal with:
Vnin
_lo=
Vin
_hi
Vnin
_hi=
Vin
_lo
and further that the transistors Q
1
and Q
2
are substantially equal, so that:
VBE=VBE
2_lo=
VBE
1_hi
VCE=VCE
2_lo=
VCE
1_hi
Pd
2_hi=
Pd
1_lo=0
Pd=Pd
2_lo=
Pd
1_hi
leading to:
Pd
1_hi−
Pd
1_lo=
Pd=I
1
·(
VCC−R·I
1
−(
Vin
_hi−
VBE
))  eq. 1
Pd
2_hi−
Pd
2_lo=
−Pd=−I
1
·(
VCC−R·I
1
−(
Vin
_hi−
VBE
))  eq. 2,
whereby Pd represents the power dissipation of either transistor Q
1
or Q
2
when switched on.
FIG. 2
shows a thermal representation of the two transistors Q
1
and Q
2
in the differential amplifier of FIG.
1
. In analogy to the ‘electrical world’, the thermal representation of the power dissipation Pd by the transistors Q
1
and Q
2
can be represented as current sources Pd1 and Pd2 respectively feeding currents into an RC network. Thermal resistors Rth correspond to ohmic resistors, thermal capacitances Cth correspond to electrical capacitances, and the temperature corresponds to a voltage. Therefore, Ohm's law (V=I·R) can be represented thermally as: Temp=Pd·Rth.
A resistor Rth1 represents the thermal flow between the transistors Q
1
and Q
2
. Thermal resistors Rth2 in parallel to thermal capacitances Cth represent the thermal flow of the transistors towards the ambient world, whereby the thermal capacitances Cth reflect the limited speed of temperature distribution. When the transistors Q
1
and Q
2
change their power dissipation Pd, the actual temperature of the transistors cannot follow immediately, but will follow in some sort of low pass function with a thermal time constant Tth. For the sake of simplicity, it is assumed that transistors Q
1
and Q
2
are substantially equal and built up accordingly, so that each transistor has the thermal resistor Rth2 in parallel to the thermal capacitances Cth, thus representing the thermal flow towards the ambient world.
In the logical “low” state (with IN=low and NIN=high, thus leading to transistor Q
1
being off and the power dissipation Pd1_lo thereof being zero, Pd1_lo=0), the following equations can be given:
Temp2_lo
=
Pd2_lo
·
(
Rth2
&RightDoubleB

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