Communications: electrical – Digital comparator systems
Patent
1975-08-12
1977-01-04
Atkinson, Charles E.
Communications: electrical
Digital comparator systems
3401461AL, G06F 1112
Patent
active
040017796
ABSTRACT:
Received N pseudo random code words and one all logic "0" coded word are stored in a register one code word at a time. An N stage shift register and logic circuitry coupled to each stage of the shift register generate reference N pseudo random code words and one all logic "0" coded word with the bits of all the generated coded words being compared in an EXCLUSIVE OR gate with corresponding bits of a received coded word. The result of the comparison is coupled in common to a largest amplitude value detector which produces a strobe pulse when the amplitude value or the result of the comparison is greater than a preceding largest amplitude value detected and stored. An N stage holding shift register has each stage coupled to the output of the logic circuitry. The strobe pulse clocks the holding register to transfer the generated code word that resulted in the production of the strobe pulse to the holding register. The contents of the holding register are up-dated each time a strobe pulse is generated during a decoding cycle. At the end of the decoding cycle, the contents of the shift register are serially read out as an error free corrected code word for that one of the received code words which produced the largest amplitude value during the decoding cycle.
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Atkinson Charles E.
Hill Alfred C.
International Telephone and Telegraph Corporation
O'Halloran John T.
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